Patents by Inventor Nobuo Sasaki

Nobuo Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020050998
    Abstract: There is provided an apparatus including a plurality of processors 20, which generates a plurality of candidate status variable values as a candidate of status variable value at which the status of object image is fixed and which selects a status variable value having the highest consistency with the condition from among them, and an influence controller 10 obtains the status variable value from each processor to broadcast the obtained status variable value to all processors at the same time. Since each processor selects a status variable value having the highest consistency with the condition from among the plurality of candidates, an appropriate image can be obtained. Moreover, the processor can generate the status variable value at the next point in consideration of the status variable values of all processors sent from the influence controller 80 as to obtain an image in which a plurality of objects is influenced each other.
    Type: Application
    Filed: August 21, 2001
    Publication date: May 2, 2002
    Inventor: Nobuo Sasaki
  • Patent number: 6373491
    Abstract: An image processing device and method for processing an image defined by a combination of unit graphic forms or polygons are provided with an interpolated line completion unit which determines an interpolated line which is the line that interpolates a space between two vertices from an interpolation vector used to determine a line interpolating a space between a given vertex and another vertex among vertices of the unit graphic forms and from the coordinates of those vertices. An interpolated point computation unit is provided which determines as vertices of sub-unit graphic forms or subpolygons into which the polygons are to be split by the processing image device, interpolated points which are the points on the interpolated line. The interpolated line is a Bezier curve.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: April 16, 2002
    Assignee: Sony Computer Entertainment, Inc.
    Inventor: Nobuo Sasaki
  • Publication number: 20020031876
    Abstract: An a-Si film is patterned into a linear shape (ribbon shape) or island shape on a glass substrate. The upper surface of the a-Si film or the lower surface of the glass substrate is irradiated and scanned with an energy beam output continuously along the time axis from a CW laser in a direction indicated by an arrow, thereby crystallizing the a-Si film. This implements a TFT in which the transistor characteristics of the TFT are made uniform at high level, and the mobility is high particularly in a peripheral circuit region to enable high-speed driving in applications to a system-on glass and the like.
    Type: Application
    Filed: August 22, 2001
    Publication date: March 14, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Akito Hara, Fumiyo Takeuchi, Kenichi Yoshino, Nobuo Sasaki
  • Publication number: 20020005856
    Abstract: An image processing device and method for processing an image defined by a combination of unit graphic forms or polygons are provided with an interpolated line completion unit which determines an interpolated line which is the line that interpolates a space between two vertices from an interpolation vector used to determine a line interpolating a space between a given vertex and another vertex among vertices of the unit graphic forms and from the coordinates of those vertices. An interpolated point computation unit is provided which determines as vertices of sub-unit graphic forms or subpolygons into which the polygons are to be split by the processing image device, interpolated points which are the points on the interpolated line. The interpolated line is a Bezier curve.
    Type: Application
    Filed: August 29, 2001
    Publication date: January 17, 2002
    Inventor: Nobuo Sasaki
  • Publication number: 20010036851
    Abstract: A portable electronic device and an entertainment system that can give a user a sense of familiarity by generating a proper character using an identification number and by displaying it, for example, on a display means include an identification-number holding section which holds a proper identification number through a bus, which is connected to an interface to connect to a game-machine main body having a program-execution function. Input operation is performed by a player at an input-operation section. At an operation-information generation section, an operation information is generated in response to the input operation at the input-operation section. The RAM provides for use for operation information stores the operation information received from the operation-information generation section. A character-information generation section generates proper character information in accordance with the operation information and gene information when the latter is received through the game-machine main body.
    Type: Application
    Filed: May 14, 2001
    Publication date: November 1, 2001
    Inventors: Nobuo Sasaki, Akio Ohba
  • Patent number: 6254477
    Abstract: A portable electronic device and an entertainment system that can give a user a sense of familiarity by generating a proper character using an identification number and by displaying it, for example, on a display means include an identification-number holding section which holds a proper identification number through a bus, which is connected to an interface to connect to a game-machine main body having a program-execution function. Input operation is performed by a player at an input-operation section. At an operation-information generation section, an operation information is generated in response to the input operation at the input-operation section. The RAM provides for use for operation information stores the operation information received from the operation-information generation section. A character-information generation section generates proper character information in accordance with the operation information and gene information when the latter is received through the game-machine main body.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: July 3, 2001
    Assignee: Sony Computer Entertainment, Inc.
    Inventors: Nobuo Sasaki, Akio Ohba
  • Patent number: 5619159
    Abstract: A signal processing device comprises superconducting wiring for providing an output signal or a transmitted signal correctly corresponding to an input signal without increasing the temperature of the device. The signal processing device has a signal input end, a signal output end, and proper signal processing circuits interposed between the signal input and output ends. The superconducting wiring connects the signal input end with the signal output end. An output end of the wiring is open, and the length of the wiring is set to be approximately 25% of the product of the pulse width and the phase velocity of the signal transmitted through the wiring.
    Type: Grant
    Filed: August 9, 1995
    Date of Patent: April 8, 1997
    Assignee: Fujitsu Limited
    Inventors: Nobuo Sasaki, Toru Ishigaki
  • Patent number: 5276010
    Abstract: A process for producing an oxide crystalline thin film having a structure in which atomic layers having different chemical compositions are laminated along the film thickness direction, the process including the steps of depositing amorphous atomic layers on a substrate, layer by layer and heating the amorphous deposit to crystallize the deposit, the respective amorphous atomic layers having the same chemical compositions as those of the corresponding atomic layers of the oxide crystal structure and being stacked in an order corresponding to the atomic lamination of the crystal structure.
    Type: Grant
    Filed: February 15, 1991
    Date of Patent: January 4, 1994
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 5241209
    Abstract: A semiconductor device having a semiconductor substrate or an insulation layer, an integrated circuit on each of the opposite sides, or main surfaces, of the semiconductor substrate or insulation layer, and a path for an ultrasound signal interconnecting the integrated circuits. The path is afforded by an ultrasonic transducer on each of the opposite sides of the semiconductor substrate or insulation layer. A plurality of paths may be provided in the same semiconductor substrate or insulation layer without crosstalk by transmitting ultrasound signals having different frequencies through the respective paths. The paths may be one-way or two-way. The ultrasonic transducers each contain a piezoelectric material; the thickness of the piezoelectric material in the ultrasonic transducer, at least on the receiver side in each path, is such that the resonant frequency of the ultrasonic transducer corresponds to the frequency of the ultrasound signal signal transmitted through the path.
    Type: Grant
    Filed: July 24, 1991
    Date of Patent: August 31, 1993
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 5231077
    Abstract: A method for fabricating an active device comprises the steps of injecting particles into a single crystal substrate of a semiconductor material at a predetermined depth from the surface, annealing the substrate that contains the particles to form an insulator layer within the substrate, generally in correspondence to the predetermined depth, the step of annealing including a step of forming a single crystal semiconductor layer of a semiconductor material identical in composition with the substrate, on the insulator layer that is formed by the annealing, starting a deposition of a layer of an oxide superconductor on the semiconductor layer, growing the oxide superconductor layer while maintaining an epitaxial relationship with respect to the substrate; and converting the semiconductor layer to an oxide layer simultaneously to the growth of the oxide superconductor layer.
    Type: Grant
    Filed: August 8, 1991
    Date of Patent: July 27, 1993
    Assignee: Nobuo Sasaki
    Inventor: Nobuo Sasaki
  • Patent number: 5065348
    Abstract: A free curved surface generating system and method in which a plurality of cross sectional curves representing cross sectional shapes in an x-y coordinate system are generated, the plurality of cross sectional curves are arranged at desired positions in the x-y-z coordinate system, respectively, and thereafter a curved surface is formed between mutually adjacent cross sectional curves through an interpolation to generate the free curved surface are disclosed.
    Type: Grant
    Filed: February 14, 1991
    Date of Patent: November 12, 1991
    Assignee: Sony Corporation
    Inventors: Tetsuzo Kuragano, Akira Suzuki, Nobuo Sasaki
  • Patent number: 4866631
    Abstract: A method for generating offset surface data representing a tool path of a tool traversing patches which are mutually adjoining at boundary lines where there is no continuity of the osculating planes. The offset surface data is interpolated for the parts of the surface at which the offset surface data become mutually discontinuous at the boundary lines or for a patch having a sharp corner. The present invention is applicable to a NC (Numerical Control) machining center which can control a machine tool so as to prevent excessive milling by the tool at the discontinuous parts of the offset surface.
    Type: Grant
    Filed: October 19, 1987
    Date of Patent: September 12, 1989
    Assignee: Sony Corporation
    Inventors: Tetsuzo Kuragano, Nobuo Sasaki
  • Patent number: 4860217
    Abstract: A method and system for effecting a transformation of video image on a video screen applicable to a system for producing a special visual effect on, e.g., a television screen, in which a two-dimensional address plane is defined within a memory area, input video image is stored within the memory area, a cylinder shaped virtual image is placed on the address plane, a part of the address plane is wound on the cylinder shaped image, and when the cylinder shaped image is displaced along a predetermined direction on the address plane with a radius of a circle in vertical section thereof being varied with time, the address plane can be viewed as if it were turned over. If the input address data within the memory area is read out on the basis of output address data indicating the above-described displacement of the address plane, the output video image on the video screen can be viewed therethrough as if the video image were being turned over.
    Type: Grant
    Filed: December 23, 1985
    Date of Patent: August 22, 1989
    Assignee: Sony Corporation
    Inventors: Nobuo Sasaki, Tetsuzo Kuragano, Nobuyuki Minami
  • Patent number: 4791474
    Abstract: A semiconductor integrated circuit device includes basic semiconductor elements arranged regularly in lines and rows and located at intersecting points of the lines and rows and wiring conductor layers arranged among the basic semiconductor elements regularly in lines and rows. In this semiconductor integrated circuit device, according to a desired logic operation, wiring conductor layers are cut or contact holes are formed on the wiring conductor layers to form wiring metal layers and connect the basic semiconductor elements to one another, so that an integrated circuit chip capable of performing the desired logic operation is obtained.
    Type: Grant
    Filed: December 8, 1987
    Date of Patent: December 13, 1988
    Assignee: Fujitsu Limited
    Inventors: Yoshihide Sugiura, Hiroaki Ichikawa, Nobutake Matsumura, Nobuo Sasaki
  • Patent number: 4789931
    Abstract: A system for establishing data defining a path for machining tool such as a three-axes milling machine tool. The machining tool path is established within a three-dimensional rectangular coordinate system which corresponds to a machine coordinate system for numerical control. The tool path is established along a first coordinate axis. The tool path is shifted to an adjacent path along the first coordinate axis in a second axis direction. The shifting pitch of the path corresponds to the interval of said path along the first the coordinate axis. The tool is shifted in third axis direction during travel along the path defined in the first and second axis direction.
    Type: Grant
    Filed: September 1, 1987
    Date of Patent: December 6, 1988
    Assignee: Sony Corporation
    Inventors: Tetsuzo Kuragano, Nobuo Sasaki
  • Patent number: 4761677
    Abstract: A reliable multilevel interconnection structure is attained by using polyacetylene layers. Nondoped polyacetylene is dielectric but is conductive when it is doped with an impurity such as AsF.sub.5, which makes it possible to eliminate the necessity of opening a contact hole or through hole in an insulating layer in a process for manufacturing a multilevel interconnection structure so that a disconnection and/or short circuit does not occur due to the evenness of the layers even if the layer of numbers is increased.
    Type: Grant
    Filed: January 22, 1987
    Date of Patent: August 2, 1988
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4665419
    Abstract: A semiconductor device, particularly, an SOS type MOS IC, has semiconductor islands for elements (i.e., active regions). An insulator region isolating the islands includes stripe portions and wide portions at points where the stripe portions join. The stripe portions are formed by oxidizing sides of silicon island portions and have a width of from 30 nm to 2 .mu.m. At the same time, the wide portions are formed by oxidizing completely thin bridge portions of the silicon island portions. A gate electrode with a gate insulating layer runs across one of the semiconductor islands and an end of the gate electrode is present above the adjacent semiconductor island.
    Type: Grant
    Filed: April 1, 1986
    Date of Patent: May 12, 1987
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4646426
    Abstract: In the production of an MOS transistor or a one-MOS transistor one-capacitor memory cell, a gate electrode is made of aluminum, doped regions are formed by an ion-implantation method using the gate electrode as a mask, and the doped regions are annealed by a laser beam.
    Type: Grant
    Filed: April 8, 1985
    Date of Patent: March 3, 1987
    Assignee: Fujitsu Limited
    Inventor: Nobuo Sasaki
  • Patent number: 4630089
    Abstract: A semiconductor memory device including a first MIS transistor having source and drain regions formed in a substrate and a gate electrode provided on the substrate through an insulating layer; a semiconductor layer provided on the first MIS transistor through the insulating layer and being in contact with the source and drain regions of the first MIS transistor; a second MIS transistor having source and drain regions formed in the semiconductor layer and being in contact with the source and drain regions of the first MIS transistor and having a gate electrode provided on the semiconductor layer through an insulating layer; and a bit line being in contact with the source or drain region of the second MIS transistor and extended on the second MIS transistor; each gate electrode of the first and the second MIS transistors being connected with different word lines respectively, and impurities having an amount more than a required value being doped to at least one of the substrate and the semiconductor layer below
    Type: Grant
    Filed: September 26, 1984
    Date of Patent: December 16, 1986
    Assignee: Fujitsu Limited
    Inventors: Nobuo Sasaki, Yasuo Suzuki
  • Patent number: 4584025
    Abstract: A process for fabricating a substrate having a dielectrically isolated region, using energy beam recrystallization. An island of polysilicon is formed on an insulating substrate and a cap containing a dopant is coated on the entire surface of the substrate. A laser beam is irradiated through the cap, and the polysilicon is recrystallized to form a doped first single crystal silicon layer. A second single crystal silicon layer is grown over the first single crystal layer. The first single crystal layer is used as a buried layer, and a semiconductor device is fabricated in the second single crystal layer. This process avoids the existence of crystal imperfections at the boundaries of the single crystal layers.
    Type: Grant
    Filed: November 26, 1984
    Date of Patent: April 22, 1986
    Assignee: Fujitsu Limited
    Inventors: Matsuo Takaoka, Nobuo Sasaki, Seiichiro Kawamura, Osamu Hataishi