Abstract: A semiconductor memory device includes a substrate, and a plurality of layers vertically stacked over the substrate. A first layer in the plurality of layers includes an active region extending in a first direction parallel to a top surface of the substrate. The semiconductor memory device also includes a first conductive line that extends vertically in a second direction perpendicular to the top surface of the substrate and penetrates through the active region. The semiconductor memory device also includes a capacitor including a first electrode that is disposed in the active region.

Abstract: A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.

Abstract: A thin-film transistor includes an insulating substrate, a gate electrode, a first gate insulating layer, a second gate insulating layer, a semiconductor layer, an insulating protective layer, a source electrode, and a drain electrode. In the transistor, the first gate insulating layer includes an insulating material containing an organic material, the second gate insulating layer includes an inorganic insulating material, the second gate insulating layer has a thickness that is smaller than a thickness of the first gate insulating layer, and the second gate insulating layer is formed only in an area overlapping the semiconductor layer or the protective layer.

Abstract: An organic thin-film transistor includes an insulating substrate, a capacitor electrode formed on the insulating substrate, a first insulating layer covering the capacitor electrode, a gate electrode formed on the first insulating layer, a second insulating layer covering the gate electrode and the capacitor electrode, a source electrode formed on the second insulating layer, a drain electrode formed on the second insulating layer, and a semiconductor layer formed on the second insulating layer in a portion between the source electrode and the drain electrode and including an organic semiconductor material.

Abstract: A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.

Abstract: A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.

Abstract: A memory device including a substrate, a non-doped semiconductor layer, a plurality of contact portions and a metal-stacking layer is provided. The substrate includes a plurality of word lines and a plurality of isolation structures. The non-doped semiconductor layer is disposed on the substrate. The contact portions are adjacent to the non-doped semiconductor layer and in direct contact with the substrate. The metal-stacking layer is disposed on the substrate. A portion of the metal-stacking layer is disposed on the non-doped semiconductor layer and in direct contact with the contact portions.

Abstract: A structure of memory cell includes a substrate. The substrate includes a first active region, a second active region and a first shallow trench isolation (STI) structure between the first active region and the second active region, wherein the first active region is lower than the second active region. A first contact structure is disposed on the first active region. A first stack structure is on the first contact structure. A second contact structure is on the substrate with a bottom portion in the substrate at an interface between the second active region and the first STI structure. A dielectric spacer is at least on a sidewall of the first contact structure. An insulating layer is disposed on the dielectric spacer and between the second contact structure and the first contact structure with the first stack structure, wherein a dielectric constant of the dielectric spacer is lower than a dielectric constant of the insulating layer.

Abstract: A method for forming the contact structure is provided. The method includes: forming a gate structure and a first insulating layer on a substrate; performing a first etching process to form a contact hole in the first insulating layer; forming a first liner material on sidewalls and a bottom of the contact hole; performing a second etching process; forming a second liner on the sidewalls and the bottom of the contact hole; and filling a conductive material into the contact hole to form a conductive element on the substrate and in the first insulating layer. The second liner and the conductive element form a conductive contact plug, wherein a bottom surface of the conductive contact plug has a first width W1, wherein a top surface of the conductive contact plug has a second width W2, and wherein the first width W1 is greater than the second width W2.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, word lines and bit lines. The semiconductor substrate has active regions separated from one another and extending along a first direction. The word lines are formed in the semiconductor substrate. The active regions are respectively intersected with one or more of the word lines. The word lines respectively have thick portions and a narrow portion continuously extending on the thick portions along a second direction. The thick portions are located at where the word lines are intersected with the active regions. The bit lines are formed over the semiconductor substrate, and extending along a third direction intersected with the first and second directions.

Abstract: A method for fabricating a memory device includes: forming a first dielectric layer disposed on a substrate, and a first opening in the first dielectric layer; filling a lower portion of the first opening with a first conductive material layer; conformally forming a lining layer over sidewalls of an upper portion of the first opening and a top surface of the first conductive material layer; filling the upper portion of the first opening with a second conductive material layer; etching back the second conductive material layer and the lining layer to form a recess; conformally forming a protection layer on sidewalls and a bottom portion of the recess and a top surface of the first dielectric layer; forming a second opening that penetrates through the protection layer, the second conductive material layer, the lining layer and the first conductive material layer; forming a pair of contacts in the first opening.

Abstract: A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.

Abstract: An X-ray inspection apparatus includes: an X-ray emission unit for emitting an X-ray to an object; an X-ray detection unit for detecting each X-ray photon transmitted through the object by discriminating energy possessed by the photon into one or more energy region(s) in accordance with a predetermined threshold level; a storage unit for storing the object and the associated threshold level; a threshold level setting unit for referring to the storage unit to keep a threshold level for the object specified by inputted information so that the X-ray detection unit can refer to the threshold level as the predetermined threshold level; and an inspection unit for inspecting the object based on a number of photons or an amount corresponding to the number of the photons detected by the X-ray detection unit for each of the one or more energy region(s).

Abstract: A memory device including a substrate, a non-doped semiconductor layer, a plurality of contact portions and a metal-stacking layer is provided. The substrate includes a plurality of word lines and a plurality of isolation structures. The non-doped semiconductor layer is disposed on the substrate. The contact portions are adjacent to the non-doped semiconductor layer and in direct contact with the substrate. The metal-stacking layer is disposed on the substrate. A portion of the metal-stacking layer is disposed on the non-doped semiconductor layer and in direct contact with the contact portions.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes an interlayer insulating layer formed on a substrate, a conductive contact plug formed in the interlayer insulating layer, a conductive barrier structure formed on the conductive contact plug, and a capacitor structure formed on the conductive barrier structure. The area of the top surface of the conductive contact plug is smaller than the area of the bottom surface of the conductive barrier structure, and the top surface of the conductive contact plug is completely covered by the bottom surface of the conductive barrier structure.

Abstract: A method for fabricating a memory device includes: forming a first dielectric layer disposed on a substrate, and a first opening in the first dielectric layer; filling a lower portion of the first opening with a first conductive material layer; conformally forming a lining layer over sidewalls of an upper portion of the first opening and a top surface of the first conductive material layer; filling the upper portion of the first opening with a second conductive material layer; etching back the second conductive material layer and the lining layer to form a recess; conformally forming a protection layer on sidewalls and a bottom portion of the recess and a top surface of the first dielectric layer; forming a second opening that penetrates through the protection layer, the second conductive material layer, the lining layer and the first conductive material layer; forming a pair of contacts in the first opening.

Abstract: An electromagnetic wave detection module in which wiring is formed to connect each detection element of an electromagnetic wave detection means configured by arranging a plurality of detection elements for detecting an electromagnetic wave in a two-dimensional array and a predetermined connection destination outside the electromagnetic wave detection means with good manufacturability and so as not to cause trouble in the detection of an electromagnetic wave as much as possible. A detection element group includes M detection elements (M is an integer of 2 or more) arranged in the Y-axis direction is arranged in N rows (N is an integer of 2 or more) in the X-axis direction orthogonal to the Y-axis direction, and M×N wirings electrically connecting each of the M×N detection elements and a predetermined connection destination outside any one end of the electromagnetic wave detection means in the Y-axis direction are provided on the common substrate surface.

Abstract: Memory devices include a first dielectric layer disposed on a substrate. Memory devices include a pair of contacts and a dielectric portion disposed in an opening of the first dielectric layer. The pair of contacts are separated from each other by the dielectric portion. Each contact includes a first conductive portion disposed on the substrate, a second conductive portion disposed over the first conductive portion and a lining layer disposed between the first conductive portion and the second conductive portion and on a sidewall of the opening. The second conductive portion has a sidewall that is in contact with the dielectric portion and the lining layer is not located thereon. The second conductive portion has a corner in connection with the sidewall and a top surface of the second conductive portion, and a protection portion is disposed on the corner.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes an interlayer insulating layer formed on a substrate, a conductive contact plug formed in the interlayer insulating layer, a conductive barrier structure formed on the conductive contact plug, and a capacitor structure formed on the conductive barrier structure. The area of the top surface of the conductive contact plug is smaller than the area of the bottom surface of the conductive barrier structure, and the top surface of the conductive contact plug is completely covered by the bottom surface of the conductive barrier structure.

Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.