Patents by Inventor Noriaki Ikeda
Noriaki Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150179391Abstract: An X-ray inspection system of the present application is capable of blocking the effect of heat from an X-ray source, thereby making it possible to place a heat-sensitive circuit component in the same housing space as the X-ray source. The X-ray inspection system includes a housing 10 provided with an upper housing space 11, in which an X-ray source 32 housed in a cooling container 30 is placed. Due to pressure of a pump 36, a cooling medium circulates between the cooling container 30 and a heat radiating device 33, thereby suppressing the temperature rise of the cooling container 30. Since the cooling container 30 is placed in the upper housing space 11, the upper housing space 11 serves as a cooling space, suppressing the temperature rise. Therefore, heat-sensitive or heat-producing circuit components can be placed in the upper housing space 11.Type: ApplicationFiled: March 9, 2015Publication date: June 25, 2015Inventors: Noriaki IKEDA, Kazunori Yamada
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Patent number: 9001565Abstract: A memory mat (101) includes a main body portion (200) that includes a first capacitor (203A), a linear conductive film (204) that is formed between the main body portion (200) and a peripheral circuit (104), and a second capacitor (203B) that is formed to be in contact with the conductive film (204) at a bottom of the second capacitor (203B). The first capacitor (203A) is in contact with a contact layer (202) at a bottom of the first capacitor (203A).Type: GrantFiled: April 23, 2013Date of Patent: April 7, 2015Assignee: PS4 Luxco S.A.R.L.Inventor: Noriaki Ikeda
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Patent number: 8848124Abstract: According to the first aspect of the present invention, a drain electrode and a pixel electrode are electrically connected to each other on a protective film formed on a semiconductor active layer, and thereby it is possible to easily connect the drain electrode and the pixel electrode to each other and to improve a yield.Type: GrantFiled: March 27, 2012Date of Patent: September 30, 2014Assignee: Toppan Printing Co., Ltd.Inventors: Noriaki Ikeda, Chihiro Imamura, Manabu Ito
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Publication number: 20130286715Abstract: A memory mat (101) includes a main body portion (200) that includes a first capacitor (203A), a linear conductive film (204) that is formed between the main body portion (200) and a peripheral circuit (104), and a second capacitor (203B) that is formed to be in contact with the conductive film (204) at a bottom of the second capacitor (203B). The first capacitor (203A) is in contact with a contact layer (202) at a bottom of the first capacitor (203A).Type: ApplicationFiled: April 23, 2013Publication date: October 31, 2013Applicant: Elpida Memory, Inc.Inventor: Noriaki IKEDA
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Patent number: 8507356Abstract: Semiconductor device manufacturing method includes forming a first mask, having a first opening to implant ion into semiconductor substrate and being used to form first layer well, on semiconductor substrate; forming first-layer well having first and second regions by implanting first ion into semiconductor substrate using first mask; forming second mask, having second opening to implant ion into semiconductor substrate and being used to form second layer well, on semiconductor substrate; and forming second-layer well below first layer well by implanting second ion into semiconductor substrate using second mask. First region is formed closer to an edge of first-layer well than second region. Upon implanting first ion, first ion deflected by first inner wall of first mask is supplied to first region. Upon implanting second ion, second ion deflected by second inner wall of second mask is supplied to second region.Type: GrantFiled: November 16, 2011Date of Patent: August 13, 2013Assignee: Elpida Memory, Inc.Inventor: Noriaki Ikeda
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Patent number: 8487308Abstract: One embodiment of the present invention is a thin film transistor having a substrate, a gate electrode formed on the substrate, a gate insulating film, a semiconductor layer formed on the gate insulating film, a protective film formed on the semiconductor layer and the gate insulating film and having first and second opening sections which are separately and directly formed on the semiconductor layer, a source electrode formed on the protective film and electrically connected to the semiconductor layer at the first opening section of the protective film, and a drain electrode formed on the protective film and electrically connected to the semiconductor layer at the second opening section of the protective film.Type: GrantFiled: April 2, 2010Date of Patent: July 16, 2013Assignee: Toppan Printing Co., Ltd.Inventors: Noriaki Ikeda, Kodai Murata, Manabu Ito, Chihiro Miyazaki
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Publication number: 20120327227Abstract: An inspection apparatus is provided for inspecting a package having a content wrapped with a translucent packaging sheet, the package having an outline including front and rear edges and two side edges and having a seal where the packaging sheet is sealed formed inside at least one of the front and rear edges. The inspection apparatus includes a lighting disposed on one side of a gap across which the package is to be conveyed from an upstream conveyor mechanism to a downstream conveyor mechanism, a camera disposed on the other side of the gap, and an image processor for processing an image captured by the camera. The image processor is capable of obtaining a strip-shaped partial image including the seal from an entire image of the package, thereby enabling determination of whether a foreign substance is present in the partial image.Type: ApplicationFiled: February 16, 2012Publication date: December 27, 2012Inventors: Noriaki IKEDA, Isamu Hiroi
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Publication number: 20120262642Abstract: According to the first aspect of the present invention, a drain electrode and a pixel electrode are electrically connected to each other on a protective film formed on a semiconductor active layer, and thereby it is possible to easily connect the drain electrode and the pixel electrode to each other and to improve a yield.Type: ApplicationFiled: March 27, 2012Publication date: October 18, 2012Applicant: Toppan Printing Co., Ltd.Inventors: Noriaki IKEDA, Chihiro Imamura, Manabu Ito
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Publication number: 20120135582Abstract: Semiconductor device manufacturing method includes forming a first mask, having a first opening to implant ion into semiconductor substrate and being used to form first layer well, on semiconductor substrate; forming first-layer well having first and second regions by implanting first ion into semiconductor substrate using first mask; forming second mask, having second opening to implant ion into semiconductor substrate and being used to form second layer well, on semiconductor substrate; and forming second-layer well below first layer well by implanting second ion into semiconductor substrate using second mask. First region is formed closer to an edge of first-layer well than second region. Upon implanting first ion, first ion deflected by first inner wall of first mask is supplied to first region. Upon implanting second ion, second ion deflected by second inner wall of second mask is supplied to second region.Type: ApplicationFiled: November 16, 2011Publication date: May 31, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Noriaki IKEDA
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Patent number: 8188529Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: GrantFiled: January 7, 2009Date of Patent: May 29, 2012Assignee: Elpida Memory, Inc.Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda
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Patent number: 7872261Abstract: An embodiment of the present invention is an transparent thin film transistor which has an substantially transparent substrate, a gate line made of a thin film of a substantially transparent conductive material, a substantially transparent gate insulating film, a substantially transparent semiconductor active layer, a source line made of a thin film of a metal material and a drain electrode made of a thin film of a substantially transparent conductive material. In addition, the source line and the drain electrode are formed apart from each other and sandwich the substantially transparent semiconductor active layer. Moreover, at least any one of the thin film of the gate line and the thin film of the source line is stacked with a thin film of a metal material.Type: GrantFiled: February 20, 2009Date of Patent: January 18, 2011Assignee: Toppan Printing Co., Ltd.Inventor: Noriaki Ikeda
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Patent number: 7817787Abstract: According to one embodiment, a voice mail apparatus includes a voice processor which processes voice messages by a arbitrary processing gain, a gain controller which monitors a signal level of an output signal of the voice processor, and controls the processing gain of the voice processor to change the signal level into a specified level, and a processing controller which makes the gain controller to perform gain control of a learning voice by inputting a portion of the voice message into the voice processor as the learning voice when processing of the voice message is requested or based on predetermined conditions.Type: GrantFiled: November 3, 2008Date of Patent: October 19, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takahashi, Kazuharu Horiuchi, Hiroki Ida, Nobuhiro Masaki, Norimassa Niiya, Noriaki Ikeda, Norikuni Noguchi
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Publication number: 20100258805Abstract: One embodiment of the present invention is a thin film transistor having a substrate, a gate electrode formed on the substrate, a gate insulating film, a semiconductor layer formed on the gate insulating film, a protective film formed on the semiconductor layer and the gate insulating film and having first and second opening sections which are separately and directly formed on the semiconductor layer, a source electrode formed on the protective film and electrically connected to the semiconductor layer at the first opening section of the protective film, and a drain electrode formed on the protective film and electrically connected to the semiconductor layer at the second opening section of the protective film.Type: ApplicationFiled: April 2, 2010Publication date: October 14, 2010Applicant: Toppan Printing Co., Ltd.Inventors: Noriaki Ikeda, Kodai Murata, Manabu Ito, Chihiro Miyazaki
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Publication number: 20090212291Abstract: An embodiment of the present invention is an transparent thin film transistor which has an substantially transparent substrate, a gate line made of a thin film of a substantially transparent conductive material, a substantially transparent gate insulating film, a substantially transparent semiconductor active layer, a source line made of a thin film of a metal material and a drain electrode made of a thin film of a substantially transparent conductive material. In addition, the source line and the drain electrode are formed apart from each other and sandwich the substantially transparent semiconductor active layer. Moreover, at least any one of the thin film of the gate line and the thin film of the source line is stacked with a thin film of a metal material.Type: ApplicationFiled: February 20, 2009Publication date: August 27, 2009Applicant: Toppan Printing Co., Ltd.Inventor: Noriaki IKEDA
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Publication number: 20090179246Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.Type: ApplicationFiled: January 7, 2009Publication date: July 16, 2009Inventors: Yoshitaka NAKAMURA, Kenji KOMEDA, Ryota SUEWAKA, Noriaki IKEDA
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Publication number: 20090154661Abstract: According to one embodiment, a voice mail apparatus includes a first determining module which determines whether a dual tone multi frequency (DTMF) signal for identifying a processing request of the voice message is contained in a received signal by detecting and comparing a first parameter of a transmission signal from the mail box and the first parameter of the received signal to the mail box, a second determining module which determines whether the DTMF signal is contained in the received signal by detecting and comparing a second parameter of the transmission signal from the mail box and the second parameter of the received signal to the mail box, and a controller which controls execution/stop of processing of the voice message based on a determination result by the second determining module.Type: ApplicationFiled: October 22, 2008Publication date: June 18, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Noriaki Ikeda, Nobuhiro Masaki, Akira Takahashi, Norikuni Noguchi, Kazuharu Horiuchi, Hiroki Ida, Norimasa Niiya
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Publication number: 20090154660Abstract: According to one embodiment, a voice mail apparatus includes a voice processor which processes voice messages by a arbitrary processing gain, a gain controller which monitors a signal level of an output signal of the voice processor, and controls the processing gain of the voice processor to change the signal level into a specified level, and a processing controller which makes the gain controller to perform gain control of a learning voice by inputting a portion of the voice message into the voice processor as the learning voice when processing of the voice message is requested or based on predetermined conditions.Type: ApplicationFiled: November 3, 2008Publication date: June 18, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira Takahashi, Kazuharu Horiuchi, Hiroki Ida, Nobuhiro Masaki, Norimasa Niiya, Noriaki Ikeda, Norikuni Noguchi
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Patent number: 7547628Abstract: A method for manufacturing a capacitor includes depositing an interlayer insulating film on or above a plug connected to a switching element, forming a hole in the interlayer insulating film such that the opening portion of the hole is surrounded by an overhang structure and that the plug is exposed in the bottom of the hole, removing the overhang structure, forming a lower electrode on the inner surface of the deep hole, forming a dielectric on the lower electrode, and forming an upper electrode on the dielectric. The above steps prevent the formation of a gap in the capacitor, since the overhang structure as a cause of the gap is removed. The coverage by the dielectric is also prevented from being poor.Type: GrantFiled: November 13, 2006Date of Patent: June 16, 2009Assignee: Elpida Memory, Inc.Inventor: Noriaki Ikeda
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Publication number: 20080265294Abstract: The present invention provides a semiconductor device manufacturing method of a semiconductor device having a contact plug, in which a contact hole formed by a surface portion of a high-concentration N-type diffusion layer formed on a semiconductor silicon substrate surface and an interlayer insulating film is implanted with indium ions at an energy ranging from 30 to 120 keV and an implantation amount ranging from 1.0×1013/cm2 to 5.0×1014/cm2 to grow an indium-containing layer on the surface portion of the high-concentration N-type diffusion layer at the bottom of the contact hole.Type: ApplicationFiled: June 24, 2008Publication date: October 30, 2008Applicant: ELPIDA MEMORY INC.Inventor: Noriaki Ikeda
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Patent number: 7399701Abstract: The present invention provides a semiconductor device manufacturing method of a semiconductor device having a contact plug, in which a contact hole formed by a surface portion of a high-concentration N-type diffusion layer formed on a semiconductor silicon substrate surface and an interlayer insulating film is implanted with indium ions at an energy ranging from 30 to 120 keV and an implantation amount ranging from 1.0×1013/cm2 to 5.0×1014/cm2 to grow an indium-containing layer on the surface portion of the high-concentration N-type diffusion layer at the bottom of the contact hole.Type: GrantFiled: May 4, 2006Date of Patent: July 15, 2008Assignee: Elpida Memory Inc.Inventor: Noriaki Ikeda