Patents by Inventor Noriaki Ikeda

Noriaki Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200043785
    Abstract: A contact structure and a method for forming the contact structure are provided. The contact structure includes an insulating layer formed on a substrate. The contact structure includes a conductive element formed on the substrate and in the insulating layer. The contact structure includes a first liner formed in the insulating layer and on sidewalls of an upper portion of the conductive element. The contact structure includes a second liner formed on the sidewalls of the conductive element. A conductive contact plug is formed by the second liner and the conductive element. At the upper portion of the conductive element, the second liner is interposed between the conductive element and the first liner. At the lower portion of the conductive element, the second liner is interposed between the conductive element and the insulating layer.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: Huang-Nan CHEN, Noriaki IKEDA
  • Publication number: 20190319029
    Abstract: Memory devices include a first dielectric layer disposed on a substrate. Memory devices include a pair of contacts and a dielectric portion disposed in an opening of the first dielectric layer. The pair of contacts are separated from each other by the dielectric portion. Each contact includes a first conductive portion disposed on the substrate, a second conductive portion disposed over the first conductive portion and a lining layer disposed between the first conductive portion and the second conductive portion and on a sidewall of the opening. The second conductive portion has a sidewall that is in contact with the dielectric portion and the lining layer is not located thereon. The second conductive portion has a corner in connection with the sidewall and a top surface of the second conductive portion, and a protection portion is disposed on the corner.
    Type: Application
    Filed: November 7, 2018
    Publication date: October 17, 2019
    Inventors: Huang-Nan CHEN, Noriaki IKEDA
  • Publication number: 20190212464
    Abstract: An X-ray inspection apparatus includes: an X-ray emission unit for emitting an X-ray to an object; an X-ray detection unit for detecting each X-ray photon transmitted through the object by discriminating energy possessed by the photon into one or more energy region(s) in accordance with a predetermined threshold level; a storage unit for storing the object and the associated threshold level; a threshold level setting unit for referring to the storage unit to keep a threshold level for the object specified by inputted information so that the X-ray detection unit can refer to the threshold level as the predetermined threshold level; and an inspection unit for inspecting the object based on a number of photons or an amount corresponding to the number of the photons detected by the X-ray detection unit for each of the one or more energy region(s).
    Type: Application
    Filed: September 20, 2017
    Publication date: July 11, 2019
    Inventors: Noriaki IKEDA, Sachihiro NAKAGAWA
  • Publication number: 20190189942
    Abstract: An organic thin-film transistor includes an insulating substrate, a capacitor electrode formed on the insulating substrate, a first insulating layer covering the capacitor electrode, a gate electrode formed on the first insulating layer, a second insulating layer covering the gate electrode and the capacitor electrode, a source electrode formed on the second insulating layer, a drain electrode formed on the second insulating layer, and a semiconductor layer formed on the second insulating layer in a portion between the source electrode and the drain electrode and including an organic semiconductor material.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 20, 2019
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Noriaki IKEDA, Makoto NISHIZAWA
  • Patent number: 10312375
    Abstract: A thin-film transistor including an insulative substrate, a gate electrode formed on the insulative substrate, a gate insulating layer formed on the substrate and the gate electrode, a source electrode and a drain electrode forming on the gate insulating layer and spaced from each other, a semiconductor layer formed on the gate insulating layer and connected to the source electrode and the drain electrode, a semiconductor protective layer formed on the semiconductor layer, an interlayer insulating film formed on the source electrode, the drain electrode and the semiconductor protective layer, the interlayer insulating film including a fluorine compound, and an upper electrode formed on the interlayer insulating film.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 4, 2019
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Noriaki Ikeda, Makoto Nishizawa
  • Patent number: 10243157
    Abstract: A thin film transistor array includes a substrate, a gate electrode formed on the substrate, a gate insulation film covering the gate electrode, a source electrode formed on the gate insulation film, a drain electrode formed on the gate insulation film, a semiconductor layer connected to the source electrode and the drain electrode, an interlayer insulation film formed on the drain electrode and the semiconductor layer, and a pixel electrode formed on the interlayer insulation film. The interlayer insulation film has a via hole that reaches a portion of the drain electrode, and the drain electrode has a liquid repellent coating on the portion positioned in the via hole.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: March 26, 2019
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Minoru Kumagai, Noriaki Ikeda
  • Patent number: 10083906
    Abstract: A memory device and a method for manufacturing a memory device are provided. The memory device includes a semiconductor substrate having a trench, an oxide layer formed on a surface of the trench, and a buried word line formed in the trench having the oxide layer formed thereon. The oxide layer includes a first portion extending downward from a top surface of the semiconductor substrate, a second portion extending upward from a bottom portion of the trench, and a third portion formed between and adjoining the first portion and the second portion. The third portion tapers toward the second portion. The first portion of the oxide layer is located between the buried word line and the surface of the trench.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 25, 2018
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Kai Jen, Wei-Che Chang, Kazutaka Manabe, Kazuaki Takesako, Noriaki Ikeda, Yoshinori Tanaka
  • Patent number: 10074654
    Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: September 11, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe, Noriaki Ikeda, Wei-Che Chang
  • Patent number: 10043810
    Abstract: A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a plurality of isolation structures, a plurality of word lines, a plurality of bit line contacts and a plurality of buried bit lines. The isolation structures are located in the substrate and defines a plurality of active regions extending along a first direction. The word lines are located in the substrate and are extending along a second direction, the second direction intersects with the first direction. The bit line contacts are located above the isolation structures, wherein each of the bit line contacts have a diffusion region that defines a bit line side contact. The buried bit lines are located above the bit line contacts and are connected to the active region via the bit line side contact, the buried bit lines are extending along the first direction and is parallel with the plurality of active regions.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 7, 2018
    Assignee: Winbond Electronics Corp.
    Inventor: Noriaki Ikeda
  • Patent number: 9972626
    Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 15, 2018
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe, Noriaki Ikeda, Wei-Che Chang
  • Publication number: 20180026141
    Abstract: A thin-film transistor including an insulative substrate, a gate electrode formed on the insulative substrate, a gate insulating layer formed on the substrate and the gate electrode, a source electrode and a drain electrode forming on the gate insulating layer and spaced from each other, a semiconductor layer formed on the gate insulating layer and connected to the source electrode and the drain electrode, a semiconductor protective layer formed on the semiconductor layer, an interlayer insulating film formed on the source electrode, the drain electrode and the semiconductor protective layer, the interlayer insulating film including a fluorine compound, and an upper electrode formed on the interlayer insulating film.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 25, 2018
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Noriaki IKEDA, Makoto NISHIZAWA
  • Patent number: 9865424
    Abstract: An X-ray inspection system of the present application is capable of blocking the effect of heat from an X-ray source, thereby making it possible to place a heat-sensitive circuit component in the same housing space as the X-ray source. The X-ray inspection system includes a housing 10 provided with an upper housing space 11, in which an X-ray source 32 housed in a cooling container 30 is placed. Due to pressure of a pump 36, a cooling medium circulates between the cooling container 30 and a heat radiating device 33, thereby suppressing the temperature rise of the cooling container 30. Since the cooling container 30 is placed in the upper housing space 11, the upper housing space 11 serves as a cooling space, suppressing the temperature rise. Therefore, heat-sensitive or heat-producing circuit components can be placed in the upper housing space 11.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 9, 2018
    Assignee: SYSTEM SQUARE INC.
    Inventors: Noriaki Ikeda, Kazunori Yamada
  • Patent number: 9733384
    Abstract: A package inspection system is provided, where an electromagnetic-wave detection part is hardly affected by illumination light for optical detection. Below a gap 6c of a conveyor mechanism 6 for conveying a package, provided are an X-ray sensor 13 for detecting X rays transmitted through the package and an illumination part 16 for applying illumination light to the gap 6c. The X-ray sensor 13 and the illumination part 16 are separated from each other by a partition 42. A light-shielding member 43 is placed in the path of X-ray incidence to the X-ray sensor 13. The light-shielding member 43 is formed of a material that allows passage of the X rays but does not allow passage of the illumination light and is hardly deteriorated by irradiation of the X rays, e.g., a carbon sheet.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: August 15, 2017
    Assignee: System Square Inc.
    Inventors: Atsushi Suzuki, Noriaki Ikeda
  • Publication number: 20170222168
    Abstract: A thin-film transistor including a substrate, a gate electrode positioned on the substrate, a gate insulating layer positioned on the substrate and the gate electrode, a source electrode positioned on the gate insulating layer, a drain electrode positioned on the gate insulating layer, a semiconductor layer connected to the source electrode and the drain electrode, and a protective layer positioned on the semiconductor layer. The source electrode and the drain electrode each have a surface including asperities.
    Type: Application
    Filed: April 20, 2017
    Publication date: August 3, 2017
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventor: Noriaki IKEDA
  • Patent number: 9541499
    Abstract: A package inspection system includes a conveyor mechanism 6, an X-ray generator 10 applying X rays to a package W1 conveyed by the conveyor mechanism 6, an X-ray sensor 13, and an optical sensor 15. First image data showing the outline of the content of the package W1 are generated based on detection output from the X-ray sensor 13. Second image data showing the outline of the wrapping of the package W1 are generated based on detection output from an optical sensor 15. The relative position of the wrapping and the content is determined based on the first and second image data, so that failures, e.g., the content caught in a seal of the wrapping can be detected accurately. The package inspection system can accurately determine a position of a wrapping and the content of a package even if a package has a light non-transmissive wrapping.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: January 10, 2017
    Assignee: SYSTEM SQUARE INC.
    Inventor: Noriaki Ikeda
  • Publication number: 20160285019
    Abstract: A thin film transistor array includes a substrate, a gate electrode formed on the substrate, a gate insulation film covering the gate electrode, a source electrode formed on the gate insulation film, a drain electrode formed on the gate insulation film, a semiconductor layer connected to the source electrode and the drain electrode, an interlayer insulation film formed on the drain electrode and the semiconductor layer, and a pixel electrode formed on the interlayer insulation film. The interlayer insulation film has a via hole that reaches a portion of the drain electrode, and the drain electrode has a liquid repellent coating on the portion positioned in the via hole.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 29, 2016
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Minoru KUMAGAI, Noriaki IKEDA
  • Publication number: 20160033404
    Abstract: A package inspection system is provided, where an electromagnetic-wave detection part is hardly affected by illumination light for optical detection. Below a gap 6c of a conveyor mechanism 6 for conveying a package, provided are an X-ray sensor 13 for detecting X rays transmitted through the package and an illumination part 16 for applying illumination light to the gap 6c. The X-ray sensor 13 and the illumination part 16 are separated from each other by a partition 42. A light-shielding member 43 is placed in the path of X-ray incidence to the X-ray sensor 13. The light-shielding member 43 is formed of a material that allows passage of the X rays but does not allow passage of the illumination light and is hardly deteriorated by irradiation of the X rays, e.g., a carbon sheet.
    Type: Application
    Filed: October 3, 2013
    Publication date: February 4, 2016
    Inventors: Atsushi Suzuki, Noriaki Ikeda
  • Publication number: 20150249052
    Abstract: The semiconductor device according to the present invention comprises: a memory cell region formed on a semiconductor substrate; peripheral circuit regions formed at the periphery of the memory cell region; embedded wiring lines formed embedded in trench portions formed in the semiconductor substrate; and upper wiring lines formed in a layer above the memory cell region and the peripheral circuit regions, and peripheral circuits in the peripheral circuit regions are connected to the upper wiring lines by way of the embedded wiring lines.
    Type: Application
    Filed: September 6, 2013
    Publication date: September 3, 2015
    Inventor: Noriaki IKEDA
  • Publication number: 20150241341
    Abstract: A package inspection system includes a conveyor mechanism 6, an X-ray generator 10 applying X rays to a package W1 conveyed by the conveyor mechanism 6, an X-ray sensor 13, and an optical sensor 15. First image data showing the outline of the content of the package W1 are generated based on detection output from the X-ray sensor 13. Second image data showing the outline of the wrapping of the package W1 are generated based on detection output from an optical sensor 15. The relative position of the wrapping and the content is determined based on the first and second image data, so that failures, e.g., the content caught in a seal of the wrapping can be detected accurately. The package inspection system can accurately determine a position of a wrapping and the content of a package even if a package has a light non-transmissive wrapping.
    Type: Application
    Filed: April 7, 2015
    Publication date: August 27, 2015
    Inventor: Noriaki IKEDA
  • Patent number: RE46882
    Abstract: A semiconductor device comprises a memory cell region, a peripheral circuit region and a boundary region. In the memory cell region, a concave lower electrode and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A. In the boundary region, one concave lower conductive region and a foundation layer have a same uppermost surface positioned in a height of H above the plane-A.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: May 29, 2018
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Yoshitaka Nakamura, Kenji Komeda, Ryota Suewaka, Noriaki Ikeda