Patents by Inventor Norihiro Kobayashi

Norihiro Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110151643
    Abstract: A method for manufacturing a bonded wafer by forming an ion implanted layer in a bond wafer; bonding an ion implanted surface of the bond wafer to a surface of a base wafer directly or through a silicon oxide film; and performing a delamination heat treatment. After the formation of the ion implanted layer and before the bonding, a plasma treatment is carried out with respect to a bonding surface of at least one of the bond wafer and the base wafer. The delamination heat treatment is carried out at a fixed temperature by directly putting the bonded wafer into a heat-treating furnace whose furnace temperature is set to the fixed temperature less than 475° C. without a temperature increasing step.
    Type: Application
    Filed: August 4, 2009
    Publication date: June 23, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Hiroji Aga, Tohru Ishizuka
  • Publication number: 20110104870
    Abstract: A method for manufacturing a bonded wafer, including at least implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer to form an ion-implanted layer in the wafer, bonding an ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an insulator film, and then delaminating the bond wafer at the ion-implanted layer to fabricate a bonded wafer. A plasma treatment is applied to a bonding surface of one of the bond wafer and the base wafer to grow an oxide film, etching the grown oxide film is carried out, and bonding to the other wafer is performed. The method enables preventing defects by reducing particles on the bonding surface and performing strong bonding when effecting bonding directly or through the insulator film.
    Type: Application
    Filed: February 17, 2009
    Publication date: May 5, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Tohru Ishizuka, Hiroji Aga, Nobuhiko Noto
  • Patent number: 7902042
    Abstract: A method of manufacturing an SOI wafer includes a bonding step, a thinning and a bonding annealing step. Assuming refractive index n1 of SiO2 as 1.5, refractive index n2 of Si as 3.5, and optical thickness tOP of the silicon oxide film 2 and the SOI layer 15 in the infrared wavelength region as tOP=n1×t1+n2×t2, the thickness t1 of the silicon oxide film 2 and thickness t2 of the SOI layer so as to satisfy a relation of 0.1?<tOP<2?, and so as to make (t1×n1)/(t2×n2) fall within 0.2 to 3. By nuclei killer annealing carried out before the bonding annealing, density of formation of oxygen precipitate in the base wafer after the bonding annealing is adjusted to less than 1×109/cm3. This configuration successfully provides a method of manufacturing the SOI wafer having the thin silicon oxide film and the SOI layer, and being less likely to cause warping.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: March 8, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Norihiro Kobayashi, Masayuki Imai, Tatsuo Enomoto, Hiroshi Takeno
  • Patent number: 7890620
    Abstract: The monitoring technology capable of reducing total monitoring cost without degrading the monitoring capability in accordance with the configuration of the large-scale service system and quickly comprehending the state of the service system after the configuration change. A monitoring system in which information processing apparatuses constituting the service system are objects to be monitored has a monitoring manager program and a plurality of monitoring agent programs, and objects to be monitored having the same performance characteristics are sorted into the same groups. In each of the groups, parties where monitoring is carried out at a short monitoring interval and parties where the monitoring is carried out at a long monitoring interval are provided. The performance of objects to be monitored in the party of the long monitoring interval is estimated from the performance of the objects to be monitored in the party of the short monitoring interval.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: February 15, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Mineyoshi Masuda, Norihiro Kobayashi, Tomohiro Morimura
  • Patent number: 7861421
    Abstract: The present invention provides a method for measuring a rotation angle of a bonded wafer, wherein a base wafer and a bond wafer each having a notch indicative of a crystal orientation formed at an outer edge thereof are bonded to each other at a desired rotation angle by utilizing the notches, a profile of the bond wafer having a reduced film thickness is observed with respect to a bonded wafer manufactured by reducing a film thickness of the bond wafer, a positional direction of the notch of the bond wafer seen from a center of the bonded wafer is calculated by utilizing the profile, an angle formed between the calculated positional direction of the notch of the bond wafer and a positional direction of the notch of the base wafer is calculated, and a rotation angle of the base wafer and the bond wafer is measured.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: January 4, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Publication number: 20100314722
    Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.
    Type: Application
    Filed: February 19, 2009
    Publication date: December 16, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
  • Publication number: 20100132205
    Abstract: The present invention provides a method for measuring a rotation angle of a bonded wafer, wherein a base wafer and a bond wafer each having a notch indicative of a crystal orientation formed at an outer edge thereof are bonded to each other at a desired rotation angle by utilizing the notches, a profile of the bond wafer having a reduced film thickness is observed with respect to a bonded wafer manufactured by reducing a film thickness of the bond wafer, a positional direction of the notch of the bond wafer seen from a center of the bonded wafer is calculated by utilizing the profile, an angle formed between the calculated positional direction of the notch of the bond wafer and a positional direction of the notch of the base wafer is calculated, and a rotation angle of the base wafer and the bond wafer is measured.
    Type: Application
    Filed: July 3, 2008
    Publication date: June 3, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Patent number: 7721295
    Abstract: An execution multiplicity control system is provided which measures a load distribution over service objects for each case when one type of service requests are inputted into a distributed object system; calculates an effect index for when the execution multiplicity of each of the service objects is varied, based on the load distribution; measures, for each type of the service requests, the number of service requests actually inputted, to acquire a request distribution; calculates and stores a total effect index for when the execution multiplicity of each of the service objects is varied, based on the effect index and the request distribution; and controls the execution multiplicity of the service objects by applying a method of controlling the execution multiplicity of the service objects in descending order of the respective total effect indices calculated.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: May 18, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Kudo, Futoshi Haga, Norihiro Kobayashi
  • Publication number: 20100120223
    Abstract: The present invention is a method for manufacturing a bonded wafer by an ion implantation delamination method including at least the steps of, bonding a bond wafer having a micro bubble layer formed by gas ion implantation with a base wafer to be a supporting substrate, delaminating the bond wafer along the micro bubble layer as a boundary to form a thin film on the base wafer, the method comprising, cleaning the bonded wafer after delaminating the bond wafer using ozone water; performing rapid thermal anneal process under a hydrogen containing atmosphere; forming a thermal oxide film on a surface layer of the bonded wafer by subjecting to heat treatment under an oxidizing gas atmosphere and removing the thermal oxide film; subjecting to heat treatment under a non-oxidizing gas atmosphere.
    Type: Application
    Filed: July 3, 2008
    Publication date: May 13, 2010
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Hiroji Aga, Yasuo Nagaoka, Nobuhiko Noto
  • Patent number: 7521334
    Abstract: A method for producing a direct bonded wafer comprising: forming a thermal oxide film or a CVD oxide film on a surface of at least one of a bond wafer and a base wafer, and bonding the wafer to the other wafer via the oxide film; subsequently thinning the bond wafer to prepare a bonded wafer; and thereafter conducting a process of annealing the bonded wafer under an atmosphere including any one of an inert gas, hydrogen and a mixed gas of an inert gas and hydrogen so that the oxide film between the bond wafer and the base wafer is removed to bond the bond wafer directly to the base wafer. Thereby, there is provided a method for producing a direct bonded wafer in which generation of voids is reduced, and a direct bonded wafer with a low void count.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: April 21, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Toru Ishizuka, Tomohiko Ohta, Hiroji Aga, Yasuo Nagaoka
  • Publication number: 20080128851
    Abstract: A method of manufacturing an SOI wafer includes a bonding step, a thinning and a bonding annealing step. Assuming refractive index n1 of SiO2 as 1.5, refractive index n2 of Si as 3.5, and optical thickness tOP of the silicon oxide film 2 and the SOI layer 15 in the infrared wavelength region as tOP=n1×t1+n2×t2, the thickness t1 of the silicon oxide film 2 and thickness t2 of the SOI layer so as to satisfy a relation of 0.1?<tOP<2?, and so as to make (t1×n1)/(t2×n2) fall within 0.2 to 3. By nuclei killer annealing carried out before the bonding annealing, density of formation of oxygen precipitate in the base wafer after the bonding annealing is adjusted to less than 1×109/cm3. This configuration successfully provides a method of manufacturing the SOI wafer having the thin silicon oxide film and the SOI layer, and being less likely to cause warping.
    Type: Application
    Filed: September 9, 2005
    Publication date: June 5, 2008
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Norihiro Kobayashi, Masayuki Imai, Tatsuo Enomoto, Hiroshi Takeno
  • Publication number: 20080102603
    Abstract: A method for producing a direct bonded wafer comprising: forming a thermal oxide film or a CVD oxide film on a surface of at least one of a bond wafer and a base wafer, and bonding the wafer to the other wafer via the oxide film; subsequently thinning the bond wafer to prepare a bonded wafer; and thereafter conducting a process of annealing the bonded wafer under an atmosphere including any one of an inert gas, hydrogen and a mixed gas of an inert gas and hydrogen so that the oxide film between the bond wafer and the base wafer is removed to bond the bond wafer directly to the base wafer. Thereby, there is provided a method for producing a direct bonded wafer in which generation of voids is reduced, and a direct bonded wafer with a low void count.
    Type: Application
    Filed: November 29, 2005
    Publication date: May 1, 2008
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Toru Ishizuka, Tomohiko Ohta, Hiroji Aga, Yasuo Nagaoka
  • Publication number: 20070072234
    Abstract: The present invention provides a protein having a binding capacity to a plasticizer, which has been conferred with useful properties for measuring, quantifying, or concentrating a plasticizer, such as high sensitivity, low cross-reactivity, high tolerance for interferents, and high tolerance for solvents. Specifically, the present invention provides a modified protein having various properties, such as affinity for antigenic plasticizers, antigen binding capacity, cross-reactivity, tolerance for antigen-antibody reaction interferents, tolerance for enzymatic color developing reaction interferents, and tolerance for solvents, improved by gene recombination technology.
    Type: Application
    Filed: April 13, 2004
    Publication date: March 29, 2007
    Applicant: Japan EnviroChemicals, Ltd.
    Inventors: Norihiro Kobayashi, Yasuhiro Goda, Masato Hirobe
  • Patent number: 7189293
    Abstract: The present invention is a method of producing an annealed wafer wherein a silicon single crystal wafer having a diameter of 200 mm or more produced by the Czochralski (CZ) method is subjected to a high temperature heat treatment in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100–1350° C. for 10–600 minutes, and before the high temperature heat treatmen, a pre-annealing is performed at a temperature less than the temperature of the high temperature heat treatment, so that the growth of slip dislocations is suppressed by growing oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein the generation and growth of slip dislocations generated in a high temperature heat treatment are suppressed and the defect density in the wafer surface layer is lowered even in the case of a silicon single crystal wafer having a large diameter of 200 mm or more, and the annealed wafer.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: March 13, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Hiroshi Takeno, Ken Aihara
  • Patent number: 7153785
    Abstract: The present invention provides method of producing an annealed wafer wherein a silicon single crystal wafer produced by the Czochralski (CZ) method is subjected to a high temperature annealing in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100–1350° C. for 10–600 minutes, during the annealing the silicon single crystal wafer is supported by a supporting jig only in a central side region of the wafer except for 5 mm or more from a peripheral end of the wafer, and before performing the high temperature annealing, a pre-annealing is performed at a temperature less than the temperature of the high temperature annealing to grow oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein slip dislocations generated in a high temperature annealing can be suppressed even in the case of a silicon single crystal wafer having a large diameter of 300 mm or more, and provided the annealed wafer.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: December 26, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu
  • Patent number: 7147711
    Abstract: The present invention provides a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 ?·cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less, and a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 ?·cm or more and an initial interstitial oxygen concentration of 8 ppma or less and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment to form an oxide precipitate layer in a bulk portion of the wafer, as well as silicon wafers produced by these production methods.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: December 12, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masaro Tamatsuka, Wei Feig Qu, Norihiro Kobayashi
  • Publication number: 20060277295
    Abstract: The monitoring technology capable of reducing total monitoring cost without degrading the monitoring capability in accordance with the configuration of the large-scale service system and quickly comprehending the state of the service system after the configuration change. A monitoring system in which information processing apparatuses constituting the service system are objects to be monitored has a monitoring manager program and a plurality of monitoring agent programs, and objects to be monitored having the same performance characteristics are sorted into the same groups. In each of the groups, parties where monitoring is carried out at a short monitoring interval and parties where the monitoring is carried out at a long monitoring interval are provided. The performance of objects to be monitored in the party of the long monitoring interval is estimated from the performance of the objects to be monitored in the party of the short monitoring interval.
    Type: Application
    Filed: August 2, 2005
    Publication date: December 7, 2006
    Inventors: Mineyoshi Masuda, Norihiro Kobayashi, Tomohiro Morimura
  • Patent number: 7081422
    Abstract: There are provided a heat-treating method capable of suppressing generation of slip in a CZ silicon single crystal wafer having a diameter of mainly 300 mm or more even under high temperature heat treatment to annihilate grown-in defects in the vicinity of a surface of the wafer, and an annealed wafer having a DZ layer in a surface layer of the wafer and oxide precipitates in the bulk thereof at a high density which exert a high gettering effect. First heat treatment of a silicon single crystal wafer manufactured from a silicon single crystal ingot pulled by means of a Czochralski method is performed at a temperature in the range of 600 to 1100° C. to form oxide precipitates in the bulk of the wafer, and thereafter, second heat treatment is performed at a temperature in the range of 1150 to 1300° C.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: July 25, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yoshinori Hayamizu, Satoshi Tobe, Norihiro Kobayashi
  • Publication number: 20060121291
    Abstract: There are provided a heat-treating method capable of suppressing generation of slip in a CZ silicon single crystal wafer having a diameter of mainly 300 mm or more even under high temperature heat treatment to annihilate grown-in defects in the vicinity of a surface of the wafer, and an annealed wafer having a DZ layer in a surface layer of the wafer and oxide precipitates in the bulk thereof at a high density which exert a high gettering effect. First heat treatment of a silicon single crystal wafer manufactured from a silicon single crystal ingot pulled by means of a Czochralski method is performed at a temperature in the range of 600 to 1100° C. to form oxide precipitates in the bulk of the wafer, and thereafter, second heat treatment is performed at a temperature in the range of 1150 to 1300° C.
    Type: Application
    Filed: November 3, 2005
    Publication date: June 8, 2006
    Inventors: Yoshinori Hayamizu, Satoshi Tobe, Norihiro Kobayashi
  • Patent number: 7011717
    Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1–60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 ?m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 14, 2006
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka