Patents by Inventor Norihiro Kobayashi
Norihiro Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20050172303Abstract: An execution multiplicity control system is provided which measures a load distribution over service objects for each case when one type of service requests are inputted into a distributed object system; calculates an effect index for when the execution multiplicity of each of the service objects is varied, based on the load distribution; measures, for each type of the service requests, the number of service requests actually inputted, to acquire a request distribution; calculates and stores a total effect index for when the execution multiplicity of each of the service objects is varied, based on the effect index and the request distribution; and controls the execution multiplicity of the service objects by applying a method of controlling the execution multiplicity of the service objects in descending order of the respective total effect indices calculated.Type: ApplicationFiled: January 11, 2005Publication date: August 4, 2005Applicant: Hitachi, Ltd.Inventors: Yutaka Kudo, Futoshi Haga, Norihiro Kobayashi
-
Patent number: 6878645Abstract: Provided is a process for manufacturing a silicon wafer employing heat treatment which is applied on the silicon wafer in inert gas atmosphere represented by Ar annealing to annihilate Grown-in defects in a surface layer region of the silicon wafer as well as to cause no degradation of haze and micro-roughness on a surface thereof. In a process for manufacturing a silicon wafer having a step of heat treating the silicon wafer in inert gas atmosphere, using a purge box with which the silicon wafer heat treated in the inert gas atmosphere can be unloaded to outside a reaction tube of a heat treatment furnace without being put into contact with the open air, the purge box is filled with mixed gas of nitrogen and oxygen or 100% oxygen gas, and the heat treated silicon wafer is unloaded into the purge box.Type: GrantFiled: July 6, 2001Date of Patent: April 12, 2005Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Shoji Akiyama, Masaro Tamatsuka, Masaru Shinomiya, Yuichi Matsumoto
-
Publication number: 20050025691Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 ?m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.Type: ApplicationFiled: August 31, 2004Publication date: February 3, 2005Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
-
Patent number: 6844209Abstract: A semiconductor device includes a semiconductor chip carrying a plurality of contact electrodes on a principal surface thereof, wherein the contact electrodes are arranged symmetrically about an axis of symmetry according to the types of the contact electrodes.Type: GrantFiled: December 10, 2002Date of Patent: January 18, 2005Assignee: Fujitsu LimitedInventors: Naoto Yamada, Norihiro Kobayashi
-
Patent number: 6841450Abstract: The present invention provides an annealed wafer manufacturing method using a heat treatment method causing no change in resistivity of a wafer surface even when a silicon wafer having boron deposited on a surface thereof from an environment is subjected to heat treatment in an insert gas atmosphere and enabling the heat treatment in an ordinary diffusion furnace not requiring a sealed structure for increasing airtightness nor any specific facility such as explosion-proof facility. The present invention also provides an annealed wafer in which a boron concentration in the vicinity of a surface thereof is constant and crystal defects are annihilated.Type: GrantFiled: September 18, 2001Date of Patent: January 11, 2005Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Makoto Iida
-
Publication number: 20040231759Abstract: The present invention is a method of producing an annealed wafer wherein a silicon single crystal wafer having a diameter of 200 mm or more produced by the Czochralski (CZ) method is subjected to a high temperature heat treatment in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100-1350° C. for 10-600 minutes, and before the high temperature heat treatmen, a pre-annealing is performed at a temperature less than the temperature of the high temperature heat treatment, so that the growth of slip dislocations is suppressed by growing oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein the generation and growth of slip dislocations generated in a high temperature heat treatment are suppressed and the defect density in the wafer surface layer is lowered even in the case of a silicon single crystal wafer having a large diameter of 200 mm or more, and the annealed wafer.Type: ApplicationFiled: December 24, 2003Publication date: November 25, 2004Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu, Hiroshi Takeno, Ken Aihara
-
Patent number: 6809015Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 &mgr;m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.Type: GrantFiled: January 9, 2003Date of Patent: October 26, 2004Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
-
Patent number: 6805743Abstract: According to the present invention, there are provided a method for producing a silicon single crystal wafer which contains oxygen induced defects by subjecting a silicon single crystal wafer containing interstitial oxygen to a heat treatment wherein the heat treatment includes at least a step of performing a heat treatment using a resistance-heating type heat treatment furnace and a step of performing a heat treatment using a rapid heating and rapid cooling apparatus, and a silicon single crystal wafer produced by the method. There can be provided a method for producing a silicon single crystal wafer which has a DZ layer of higher quality compared with a conventional wafer in a wafer surface layer part and has oxygen induced defects at a sufficient density in a bulk part and the silicon single crystal wafer.Type: GrantFiled: January 24, 2003Date of Patent: October 19, 2004Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya
-
Patent number: 6806199Abstract: There are provided a manufacturing process for a mirror finished silicon wafer capable of manufacturing a mirror finished silicon wafer, having an excellent quality in which grown-in crystal defects are annihilated by heat-treating the silicon mirror finished wafer in a heat treatment in a gas atmosphere of high safety at a lower cost without selection of a heat treatment furnace for use in the heat treatment, a mirror finished silicon wafer having an excellent quality, and a heat treatment furnace preferably used in the manufacturing process.Type: GrantFiled: November 16, 2001Date of Patent: October 19, 2004Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Shoji Akiyama
-
Publication number: 20040192071Abstract: The present invention provides method of producing an annealed wafer wherein a silicon single crystal wafer produced by the Czochralski (CZ) method is subjected to a high temperature annealing in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100-1350° C. for 10-600 minutes, during the annealing the silicon single crystal wafer is supported by a supporting jig only in a central side region of the wafer except for 5 mm or more from a peripheral end of the wafer, and before performing the high temperature annealing, a pre-annealing is performed at a temperature less than the temperature of the high temperature annealing to grow oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein slip dislocations generated in a high temperature annealing can be suppressed even in the case of a silicon single crystal wafer having a large diameter of 300 mm or more, and provided the annealed wafer.Type: ApplicationFiled: February 23, 2004Publication date: September 30, 2004Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feing Qu
-
Publication number: 20040023518Abstract: Provided is a process for manufacturing a silicon wafer employing heat treatment which is applied on the silicon wafer in inert gas atmosphere represented by Ar annealing to annihilate Grown-in defects in a surface layer region of the silicon wafer as well as to cause no degradation of haze and micro-roughness on a surface thereof. In a process for manufacturing a silicon wafer having a step of heat treating the silicon wafer in inert gas atmosphere, using a purge box with which the silicon wafer heat treated in the inert gas atmosphere can be unloaded to outside a reaction tube of a heat treatment furnace without being put into contact with the open air, the purge box is filled with mixed gas of nitrogen and oxygen or 100% oxygen gas, and the heat treated silicon wafer is unloaded into the purge box.Type: ApplicationFiled: January 10, 2003Publication date: February 5, 2004Inventors: Norihiro Kobayashi, Shoji Akiyama, Masaro Tamatsuka, Masaru Shinomiya, Yuichi Matsumoto
-
Publication number: 20040003769Abstract: The present invention provides a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 &OHgr;·cm or more and an initial interstitial oxygen concentration of 10 to 25 ppma and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment so that a residual interstitial oxygen concentration in the wafer should become 8 ppma or less, and a method for producing a silicon wafer, which comprises growing a silicon single crystal ingot having a resistivity of 100 &OHgr;·cm or more and an initial interstitial oxygen concentration of 8 ppma or less and doped with nitrogen by the Czochralski method, processing the silicon single crystal ingot into a wafer, and subjecting the wafer to a heat treatment to form an oxide precipitate layer in a bulk portion of the wafer, as well as silicon wafers produced by these production methods.Type: ApplicationFiled: March 18, 2003Publication date: January 8, 2004Inventors: Masaro Tamatsuka, Wei Feig Qu, Norihiro Kobayashi
-
Patent number: 6670261Abstract: There is provided a manufacturing process for an annealed wafer capable of reducing boron contamination occurring while annealing is performed in a state where a wafer surface after cleaning is exposed to a gas in Ar atmosphere to suppress a change in resistivity due to an increase in a boron concentration in the vicinity of the wafer surface after annealing and manufacture an annealed wafer in which a difference in a boron concentration between a surface layer portion thereof and a bulk portion thereof is essentially not a problem even if a silicon wafer having a comparative low boron concentration (1×1016 atoms/cm3 or less) is used as the annealed wafer. The manufacturing process for an annealed wafer comprises: cleaning a silicon wafer; and loading the silicon wafer into a heat treatment furnace to heat-treat the silicon wafer in an Ar atmosphere, wherein an aqueous solution including hydrofluoric acid is used as a final cleaning liquid in the cleaning.Type: GrantFiled: November 28, 2001Date of Patent: December 30, 2003Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Shoji Akiyama, Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya
-
Publication number: 20030196588Abstract: A silicon boat for supporting a silicon wafer during a heat treatment of the wafer, wherein a protective film consisting of a thermal oxide film is directly formed on a surface of the boat. A silicon boat is left in argon, hydrogen or a mixed gas of argon and hydrogen within a temperature range of 1000° C. or higher for 10 minutes or more to remove a native oxide film on the surface of the boat and then subjected to a heat treatment in an atmosphere containing oxygen to grow a protective film consisting of an oxide film on the surface of the boat. By using this silicon boat, silicon wafers are subjected to a heat treatment in an atmosphere consisting of argon or a mixed gas of argon and hydrogen. Thus, there are provided a boat for heat treatment of wafer and a method for heat treatment of wafer, in which metal contamination is not caused in the wafer, and falling off of the protective film, damage of the wafer surface and generation of particles are prevented.Type: ApplicationFiled: January 21, 2003Publication date: October 23, 2003Inventors: Norihiro Kobayashi, Shoji Akiyama, Masaro Tamatsuka, Masaru Shinomiya
-
Publication number: 20030164139Abstract: According to the present invention, there are provided a method for producing a silicon single crystal wafer which contains oxygen induced defects by subjecting a silicon single crystal wafer containing interstitial oxygen to a heat treatment wherein the heat treatment includes at least a step of performing a heat treatment using a resistance-heating type heat treatment furnace and a step of performing a heat treatment using a rapid heating and rapid cooling apparatus, and a silicon single crystal wafer produced by the method. There can be provided a method for producing a silicon single crystal wafer which has a DZ layer of higher quality compared with a conventional wafer in a wafer surface layer part and has oxygen induced defects at a sufficient density in a bulk part and the silicon single crystal wafer.Type: ApplicationFiled: January 24, 2003Publication date: September 4, 2003Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya
-
Publication number: 20030104709Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 &mgr;m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.Type: ApplicationFiled: January 9, 2003Publication date: June 5, 2003Applicant: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
-
Patent number: 6573159Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 &mgr;m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.Type: GrantFiled: August 14, 2000Date of Patent: June 3, 2003Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Shoji Akiyama, Yuuichi Matsumoto, Masaro Tamatsuka
-
Publication number: 20030085469Abstract: A semiconductor device includes a semiconductor chip carrying a plurality of contact electrodes on a principal surface thereof, wherein the contact electrodes are arranged symmetrically about an axis of symmetry according to the types of the contact electrodes.Type: ApplicationFiled: December 10, 2002Publication date: May 8, 2003Applicant: FUJITSU LIMITEDInventors: Naoto Yamada, Norihiro Kobayashi
-
Patent number: 6551398Abstract: There is disclosed a heat treatment method for a silicon monocrystal wafer comprising the steps of heat-treating in a reducing atmosphere a silicon monocrystal wafer manufactured by growing a silicon monocrystal ingot by Czochralski method wherein a wafer obtained from a silicon monocrystal ingot having oxygen concentration of 16 ppma or less which is manufactured by pulling at a growth rate of 0.6 mm/min or more, and in which COPs exist in high density is subjected to anneal heat treatment at 1200° C. or above for one second or more through use of a rapid heating/rapid cooling apparatus, or at 1200° C. or above for 30 minutes or more through use of a batchwise heat treatment furnace, and no defect silicon monocrystal wafer obtained with the method.Type: GrantFiled: December 16, 1998Date of Patent: April 22, 2003Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Takao Abe, Norihiro Kobayashi, Masahiro Kato
-
Patent number: 6548907Abstract: A semiconductor device includes a semiconductor chip carrying a plurality of contact electrodes on a principal surface thereof, wherein the contact electrodes are arranged symmetrically about an axis of symmetry according to the types of the contact electrodes.Type: GrantFiled: October 15, 1999Date of Patent: April 15, 2003Assignee: Fujitsu LimitedInventors: Naoto Yamada, Norihiro Kobayashi