Patents by Inventor Noriyuki Ito

Noriyuki Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100095261
    Abstract: A apparatus includes: an acquisition section that acquires information on a plurality of paths which let signals propagate in the integrated circuit in descending order of propagation time; a path capability distribution calculation section that calculates, based on the acquired information on the plurality of paths, path capability distribution; an integrated circuit capability distribution calculation section that performs a statistical operation based on the path capability distribution and on first integrated circuit capability distribution, and determines the result of the statistical operation as second integrated circuit capability distribution; and an evaluation section that calculates a parameter representing a difference between the first integrated circuit capability distribution and the second integrated circuit capability distribution, and repeats the process of the acquisition section, the process of the path capability distribution calculation section, and the process of the integrated circuit
    Type: Application
    Filed: December 8, 2009
    Publication date: April 15, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Noriyuki Ito
  • Publication number: 20100080599
    Abstract: The image forming apparatus has a heat member for heating an unfixed image and is configured so that a longitudinal center of the heat member becomes a conveyance center of the recording material, the image forming apparatus including a central portion temperature detection part adjacent to the conveyance center, an end portion temperature detection part for detecting an end portion temperature of the heat member, and a width detection part for detecting a lateral width of the recording material, wherein the width detection part is disposed at a side opposite to a side at which the end portion temperature detection part is disposed with respect to the conveyance center position of the recording material. The image forming apparatus achieves the control for error setting of the recording material based on the width detection part and the end portion temperature detection part.
    Type: Application
    Filed: December 4, 2009
    Publication date: April 1, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Noriyuki ITO, Kenichi OGAWA, Rikuo KAWAKAMI
  • Patent number: 7650091
    Abstract: An image forming apparatus has a heat member configured so that a longitudinal center becomes a conveyance center of the recording material, the apparatus also having a central portion temperature detection part for detecting a temperature of the heat member corresponding to the conveyance center or adjacent thereto, a one side end portion temperature detection part for detecting one end portion temperature at one side in a longitudinal direction of the heat member, and an other side end portion temperature detection part for detecting an other end portion temperature on the other side in the longitudinal direction of the heat member, and a control part for controlling the image forming apparatus based on heat member temperature information detected by the central portion temperature detection part, the one side end portion temperature detection part, and the other side end portion temperature detection part.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: January 19, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Noriyuki Ito, Kenichi Ogawa, Rikuo Kawakami
  • Patent number: 7617431
    Abstract: The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual increase in the frequency of an operational clock pulse fed to an integrated circuit belongs. The apparatus obtains information on latch in which an error is caused with the RC of the maximal incidence, with reference to a mapping table that describes the mapping relationship between an RC and a latch. The apparatus extracts a circuit portion in which an error can be captured with the region code of the maximal incidence by exhaustively tracing back circuit portions connected with each obtained latch, from the latch to the latch described in the mapping table. The apparatus gives delay defects to the input and the output pin of each of logic elements included in the extracted circuit portion, generates test patterns for detecting the given delay defects, and performs delay tests.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: November 10, 2009
    Assignee: Fujitsu Limited
    Inventor: Noriyuki Ito
  • Publication number: 20090214830
    Abstract: To provide a waterproofing method for architectures in which while ensuring there is no peeling of the waterproof coating from the substrate and no cracking of the coating, there is also superior workability and no application of an adhesive to the substrate. To carry out waterproofing with a sheet for waterproofing comprising a layered structure of an air-releasing layer comprising a non-adhesive film or sheet having pores and an adhesive layer, wherein at least a part of the air-releasing layer and/or the adhesive layer protrudes from the layered structure.
    Type: Application
    Filed: April 21, 2006
    Publication date: August 27, 2009
    Applicant: SIKA TECHNOLOGY AG
    Inventors: Noriyuki Ito, Yoshinori Mitsui
  • Publication number: 20090206694
    Abstract: A brush holder includes terminals and a holder body, wherein each terminal includes a pair of connecting terminals provided to sandwich a cut-off portion in which the conducting path is cut to mount an electrical component for connecting the component in series with the conducting path, and a shorting path forming portion connecting the connecting terminal provided at the direct current source side with the brush to short the cut-off portion, wherein the holder body has an opening, from which the shorting path forming portion are exposed, for cutting the shorting path forming portion with the terminals held by the holder body.
    Type: Application
    Filed: February 6, 2009
    Publication date: August 20, 2009
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Tsukasa KAMIYA, Noriyuki Ito
  • Patent number: 7559042
    Abstract: To provide a layout evaluating apparatus that can determine the feasibility of a layout from information only about a netlist, the layout evaluating apparatus is made to comprise a first individual index value generating unit for generating first individual index values, a second individual index value generating unit for generating second individual index values, a correlation extracting unit for generating an evaluation expression, which is an evaluation expression for calculating a second index value from the second individual index values and by which the second index value and its block size have a correlation, and a layout evaluating unit for identifying a range where the second index value and its block size have a correlation and for determining that a layout is possible if the first index value, which is obtained by substituting the first individual index values into the evaluation expression as a replacement for the second individual index values, is included in the correlation range.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: July 7, 2009
    Assignee: Fujitsu Limited
    Inventor: Noriyuki Ito
  • Publication number: 20090148899
    Abstract: The present invention relates to a method for producing an optically-active amine compound. The method is characterized by using a transaminase (A), an ?-keto acid reductase (B), and an enzyme (C), each having specific properties, in an identical reaction system to convert a ketone compound into a corresponding optically-active amine compound in which a carbon atom with an amino group bonded thereto serves as an asymmetric point. The present invention also relates to a recombinant vector for use in the method. The present invention makes it possible to efficiently produce an optically-active amine compound.
    Type: Application
    Filed: May 28, 2007
    Publication date: June 11, 2009
    Inventors: Shigeru Kawano, Noriyuki Ito, Yoshihiko Yasohara
  • Patent number: 7510801
    Abstract: There is provided an alkaline battery produced by sealing in an outer package body: a positive mixture containing at least one selected from manganese dioxide and a nickel oxide, a conducting agent, and an alkaline electrolytic solution (A) containing potassium hydroxide; a separator; and a negative mixture containing zinc alloy powder, a gelling agent, and an alkaline electrolytic solution (B) containing potassium hydroxide where a concentration of potassium hydroxide of the alkaline electrolytic solution (A) is 45 wt % or more, and a concentration of potassium hydroxide of the alkaline electrolytic solution (B) is 35 wt % or less. Because of this, an alkaline battery can be provided, which has desirable load characteristics, prevents the generation of gas, prevents a decrease in a storage property due to the reaction with an electrolytic solution, and has heat generation behavior suppressed at a time of occurrence of a short-circuit.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: March 31, 2009
    Assignee: Hitachi Maxell, Ltd.
    Inventors: Noriyuki Ito, Minajuro Ushijima, Shinichi Iwamoto, Tetsuo Izu
  • Publication number: 20080285900
    Abstract: A motor includes a bearing and a bearing holder. The bearing is employed for rotatably supporting a motor shaft. The bearing holder is formed of a resin material and adapted to retain the bearing. Further, the bearing holder includes a cylindrical portion to which the bearing is press-fitted and a planar portion which is formed integrally with the cylindrical portion and is adapted to be arranged perpendicularly to the motor shaft. The cylindrical portion includes a first slit extending in an axial direction. The planar portion includes a second slit extending continuously with the first slit of the cylindrical portion.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 20, 2008
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventor: Noriyuki ITO
  • Publication number: 20080240803
    Abstract: The image forming apparatus has a heat member for heating an unfixed image and is configured so that a longitudinal center of the heat member becomes a conveyance center of the recording material, the image forming apparatus including a central portion temperature detection part adjacent to the conveyance center, an end portion temperature detection part for detecting an end portion temperature of the heat member, and a width detection part for detecting a lateral width of the recording material, wherein the width detection part is disposed at a side opposite to a side at which the end portion temperature detection part is disposed with respect to the conveyance center position of the recording material. The image forming apparatus achieves the control for error setting of the recording material based on the width detection part and the end portion temperature detection part.
    Type: Application
    Filed: June 5, 2008
    Publication date: October 2, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: NORIYUKI ITO, KENICHI OGAWA, RIKUO KAWAKAMI
  • Publication number: 20080184179
    Abstract: Shielded clock wiring used in an integrated circuit is designed by storing a table of identifiers of shielded clock wiring usable in the integrated circuit, storing dividing rule information in correspondence with each identifier, describing a way of dividing the shielded clock wiring indicated by the each identifier; inputting a wiring layer of a shielded clock wiring of a wiring request, inputting an identifier of the shielded clock wiring of the wiring request and inputting a starting point and an end point of the shielded clock wiring of the wiring request; specifying a dividing rule of the shielded clock wiring indicated by the identifier; and judging whether to permit the shielded clock wiring of the wiring request, by judging whether shielded clock wiring resulting from division based on the dividing rule is spatially permissible.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 31, 2008
    Inventor: Noriyuki ITO
  • Patent number: 7397488
    Abstract: The image forming apparatus has a heat member for heating an unfixed image and is configured so that a longitudinal center of the heat member becomes a conveyance center of the recording material, the image forming apparatus including a central portion temperature detection part adjacent to the conveyance center, an end portion temperature detection part for detecting an end portion temperature of the heat member, and a width detection part for detecting a lateral width of the recording material, wherein the width detection part is disposed at a side opposite to a side at which the end portion temperature detection part is disposed with respect to the conveyance center position of the recording material. The image forming apparatus achieves the control for error setting of the recording material based on the width detection part and the end portion temperature detection part.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: July 8, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Noriyuki Ito, Kenichi Ogawa, Rikuo Kawakami
  • Publication number: 20080160402
    Abstract: There is provided an alkaline battery produced by sealing in an outer package body: a positive mixture containing at least one selected from manganese dioxide and a nickel oxide, a conducting agent, and an alkaline electrolytic solution (A) containing potassium hydroxide; a separator; and a negative mixture containing zinc alloy powder, a gelling agent, and an alkaline electrolytic solution (B) containing potassium hydroxide where a concentration of potassium hydroxide of the alkaline electrolytic solution (A) is 45 wt % or more, and a concentration of potassium hydroxide of the alkaline electrolytic solution (B) is 35 wt % or less. Because of this, an alkaline battery can be provided, which has desirable load characteristics, prevents the generation of gas, prevents a decrease in a storage property due to the reaction with an electrolytic solution, and has heat generation behavior suppressed at a time of occurrence of a short-circuit.
    Type: Application
    Filed: February 28, 2008
    Publication date: July 3, 2008
    Inventors: Noriyuki ITO, Minajuro Ushijima, Shinichi Iwamoto, Tetsuo Izu
  • Publication number: 20080160403
    Abstract: There is provided an alkaline battery produced by sealing in an outer package body: a positive mixture containing at least one selected from manganese dioxide and a nickel oxide, a conducting agent, and an alkaline electrolytic solution (A) containing potassium hydroxide; a separator; and a negative mixture containing zinc alloy powder, a gelling agent, and an alkaline electrolytic solution (B) containing potassium hydroxide where a concentration of potassium hydroxide of the alkaline electrolytic solution (A) is 45 wt % or more, and a concentration of potassium hydroxide of the alkaline electrolytic solution (B) is 35 wt % or less. Because of this, an alkaline battery can be provided, which has desirable load characteristics, prevents the generation of gas, prevents a decrease in a storage property due to the reaction with an electrolytic solution, and has heat generation behavior suppressed at a time of occurrence of a short-circuit.
    Type: Application
    Filed: February 28, 2008
    Publication date: July 3, 2008
    Inventors: Noriyuki ITO, Minajuro Ushijima, Shinichi Iwamoto, Tetsuo Izu
  • Publication number: 20080089080
    Abstract: A turn lamp includes a base housing; a light source unit incorporated with a light source and housed in the base housing; an inner housing provided with a long and solid light guide; a lens cover that covers the base housing; and a diffused reflection generator that is structured such that light from the light source leaks out long from the light guide.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 17, 2008
    Applicants: MITSUBA CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yasushi Kawaji, Noriyuki Ito, Hitoshi Kurihara, Yosuke Fukasawa, Masashi Fukui, Tatsuya Sugamoto, Hideo Hamamoto, Hirofumi Nishikawa
  • Publication number: 20080086711
    Abstract: In the present invention, a block level net list is separated from a chip level net list so that the chip level net list can be created in a form in which a block is transparent to a designer. The present invention determines a destination block for circuit elements that are described in a chip level net list and for which the destination block is not determined, and creates a final net list by reflecting the chip level net list to the block level net list based on the information on the destination block. As a net list can be created in a form in which a block is transparent to a designer for a circuit system that is required to be optimized for the entire chip, the circuit system can be efficiently optimized.
    Type: Application
    Filed: April 17, 2007
    Publication date: April 10, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Noriyuki Ito
  • Publication number: 20080072108
    Abstract: The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual increase in the frequency of an operational clock pulse fed to an integrated circuit belongs. The apparatus obtains information on latch in which an error is caused with the RC of the maximal incidence, with reference to a mapping table that describes the mapping relationship between an RC and a latch. The apparatus extracts a circuit portion in which an error can be captured with the region code of the maximal incidence by exhaustively tracing back circuit portions connected with each obtained latch, from the latch to the latch described in the mapping table. The apparatus gives delay defects to the input and the output pin of each of logic elements included in the extracted circuit portion, generates test patterns for detecting the given delay defects, and performs delay tests.
    Type: Application
    Filed: February 22, 2007
    Publication date: March 20, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Noriyuki Ito
  • Patent number: 7328422
    Abstract: A design support apparatus is provided, including control portion executes layout program to implement a position judging section which performs position judgment to check, for every net, the net being formed by a first cell to be called ‘driver’ and one or a plurality of cells driven via an output terminal of the first cell to be called ‘receiver(s)’, whether or not said driver exists outside a predetermined region for enclosing said receiver(s), and a layout section which determines a base point from an inside of said predetermined region, with respect to said net where it is judged that said driver exists outside said predetermined region, and arranges said diagonal wiring for wiring which connects said output terminal of said driver with said base point when said base point can be connected with an input terminal of said receiver by means of vertical and/or horizontal wiring.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: February 5, 2008
    Assignee: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita
  • Publication number: 20080022238
    Abstract: To provide a layout evaluating apparatus that can determine the feasibility of a layout from information only about a netlist, the layout evaluating apparatus is made to comprise a first individual index value generating unit for generating first individual index values, a second individual index value generating unit for generating second individual index values, a correlation extracting unit for generating an evaluation expression, which is an evaluation expression for calculating a second index value from the second individual index values and by which the second index value and its block size have a correlation, and a layout evaluating unit for identifying a range where the second index value and its block size have a correlation and for determining that a layout is possible if the first index value, which is obtained by substituting the first individual index values into the evaluation expression as a replacement for the second individual index values, is included in the correlation range.
    Type: Application
    Filed: November 16, 2006
    Publication date: January 24, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Noriyuki Ito