Patents by Inventor Noriyuki Ito

Noriyuki Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030077092
    Abstract: The image heating apparatus for heating an image formed on a recording material, comprising a sliding member and a supporting member for holding the sliding member and a pressure member which forms a nip part, wherein a portion of said supporting member which forms the nip part projects from a surface of the sliding member on the nip part side. The image heating apparatus can suppress a decrease in durability of a flexible rotary body.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 24, 2003
    Applicant: Canon Kabushiki Kaisha
    Inventors: Kenichi Ogawa, Michihito Yamazaki, Ken Murooka, Noriaki Tanaka, Noriyuki Ito, Yusuke Nakazono, Hiroyuki Sakakibara, Akira Kato, Hisashi Nakahara, Satoshi Nishida
  • Publication number: 20030043514
    Abstract: A read head comprises an MR element, two bias field applying layers, and two conductive layers. The two bias field applying layers are adjacent to both side portions of the MR element, and apply a bias magnetic field to the MR element along the longitudinal direction. The two conductive layers feed a sense current to the MR element, each of the conductive layers being disposed to be adjacent to one of surfaces of each of the bias field applying layers and to overlap one of surfaces of the MR element. The conductive layers are each made of a gold alloy having a resistivity of less than 22 &mgr;&OHgr;·cm and a hardness as high as or higher than the hardness of a material used for making the bias field applying layers.
    Type: Application
    Filed: July 12, 2002
    Publication date: March 6, 2003
    Applicant: TDK Corporation
    Inventors: Noriyuki Ito, Kosuke Tanaka, Koichi Terunuma
  • Publication number: 20030014720
    Abstract: When a logical block is built in an LSI logic design stage, a maximum delay value between pins of a block is set based on a designer's estimation, or information of a netlist after the netlist is generated. Pins can be grouped. A delay value in a connection between pins is represented by the largest value. Additionally, a plurality of internal memory elements within a logical block are represented by one or a plurality of internal latches. Also as a delay value between a pin and an internal latch, or between an internal latch and a pin, the largest value is selected from among a plurality of delay values, and set as a representative value.
    Type: Application
    Filed: October 31, 2001
    Publication date: January 16, 2003
    Applicant: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Yoichiro Ishikawa
  • Publication number: 20020157238
    Abstract: A magnetoresistive device comprises: an MR element; two bias field applying layers that apply a longitudinal bias magnetic field to the MR element; and two electrode layers that are located adjacent to one of the surfaces of each of the bias field applying layers and overlap one of the surfaces of the MR element. The MR element incorporates a protection layer located on a soft magnetic layer. In the method of manufacturing the magnetoresistive device, a coating layer that will be removed in a later step is formed on the protection layer in advance. Before forming the electrode layers, the coating layer and an oxide layer that is formed through natural-oxidizing part of the top surface of the coating layer are removed through etching. After the electrode layers are formed, the portion of the protection layer located in the region between the two electrode layers is oxidized, and a high resistance layer is thereby formed.
    Type: Application
    Filed: August 3, 2001
    Publication date: October 31, 2002
    Applicant: TDK Corporation
    Inventors: Koji Shimazawa, Noriyuki Ito, Koichi Terunuma
  • Patent number: 6466415
    Abstract: The invention provides a thin film magnetic head including a first pole portion having depressed portion that is formed therein. The depressed portion descends, backward within the first pole portion, at a first inclination angle &thgr;1 from a first inclination starting point P1. Then, an insulating film is filled up in the depressed portion so that it can be located up to the upper side of the surface of the first pole and have an inclined surface in the side of a medium opposing surface. Additionally, a first magnetic film of a second pole portion can have a larger saturated magnetic flux density than a second magnetic film of the second pole portion, and can include an inclined portion with a second inclination angle &thgr;2 from a second inclination starting point P2.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: October 15, 2002
    Assignee: TDK Corporation
    Inventors: Koichi Terunuma, Tetsuya Mino, Katsuya Kanakubo, Noriyuki Ito
  • Publication number: 20020126423
    Abstract: Provided are a thin film magnetic head and a method of manufacturing the same, which is capable of high density recording and obtaining stable output. The thin film magnetic head comprises an MR film sandwiched in between first and second shield layers. The first shield layer includes an inner layer, a magnetization stabilizing layer, an underlayer, and an outer layer laminated in order from the MR film. The second shield layer includes an inner layer, a magnetization stabilizing layer, an isolating layer, and an outer layer laminated in order from the MR film. The magnetization stabilizing layers are formed of antiferromagnetic material, so as to control the direction of magnetization of the inner layers.
    Type: Application
    Filed: November 26, 2001
    Publication date: September 12, 2002
    Applicant: TDK CORPORATION
    Inventors: Koichi Terunuma, Ken-ichi Takano, Noriyuki Ito
  • Patent number: 6444406
    Abstract: A method for forming a photoresist pattern, includes a step of forming a photoresist pattern having a certain width, and a step of performing thereafter ion milling with respect to side walls of the formed photoresist pattern by using an ion beam with a large incident angle so as to reduce the width of the formed photoresist pattern.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: September 3, 2002
    Assignee: TDK Corporation
    Inventors: Noriyuki Ito, Koichi Terunuma, Satoshi Tsukiyama
  • Publication number: 20020081400
    Abstract: According to the present invention, there is provided a laminated composite including an optical layer having a light reflectivity, and a latent image formation layer containing a liquid crystalline polymer material and provided on one of major surfaces of the optical layer, wherein the latent image formation layer includes at least one oriented portion in an orientation state and at least one non-oriented portion in a non-orientation state, and the oriented and non-oriented portions constitute a latent image which is unrecognizable by a direct visual observation and recognizable by a visual observation through a polarizing member. Also, according to the present invention, there is provided an information recording medium and a member of imparting a forgery-preventing characteristic including such a latent image formation layer.
    Type: Application
    Filed: November 13, 2001
    Publication date: June 27, 2002
    Applicant: Toppan Printing Co., Ltd.
    Inventors: Satoshi Gocho, Atsushi Kijima, Akira Kubo, Noriyuki Ito, Naoaki Shindo
  • Publication number: 20020055264
    Abstract: A method for forming a photoresist pattern, includes a step of forming a photoresist pattern having a certain width, and a step of performing thereafter ion milling with respect to side walls of the formed photoresist pattern by using an ion beam with a large incident angle so as to reduce the width of the formed photoresist pattern.
    Type: Application
    Filed: July 6, 2001
    Publication date: May 9, 2002
    Inventors: Noriyuki Ito, Koichi Terunuma, Satoshi Tsukiyama
  • Publication number: 20020042904
    Abstract: The present invention provides a placement/net wiring processing system using an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring.
    Type: Application
    Filed: March 20, 2001
    Publication date: April 11, 2002
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Keiko Osawa, Tomoyuki Isomura, Hiroaki Hanamitsu, Hideaki Katagiri
  • Patent number: 6364964
    Abstract: The SVMR element has a non-magnetic metallic thin-film layer, first and second ferromagnetic thin-film layers (free and pinned layers) formed to sandwich the non-magnetic metallic thin-film layer and an anti-ferromagnetic thin-film layer formed in contact with a surface of the second ferromagnetic thin-film layer. This surface is opposite to the non-magnetic metallic thin-film layer. The first ferromagnetic thin-film layer has a two-layers structure of a NiFe layer and a CoFe layer. The manufacturing method includes a step of depositing the first ferromagnetic thin-film layer, the non-magnetic metallic thin-film layer, the second ferromagnetic thin-film layer and the anti-ferromagnetic thin-film layer, and a step of annealing, thereafter, the deposited layers so that change in magnetostriction depending upon variation of a thickness of the NiFe layer becomes small.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: April 2, 2002
    Assignee: TDK Corporation
    Inventors: Tetsuro Sasaki, Noriyuki Ito, Koichi Terunuma
  • Publication number: 20020024779
    Abstract: A thin-film magnetic head with an MR element, includes an MR film, under films each having a multilayer structure with a first under layer and a second under layer laminated on the first under layer, and magnetic domain control films joined to side end faces of the MR film through the under films.
    Type: Application
    Filed: July 6, 2001
    Publication date: February 28, 2002
    Inventors: Noriyuki Ito, Koichi Terunuma, Fumihiro Hiromatsu
  • Patent number: 6240541
    Abstract: A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: May 29, 2001
    Assignee: Fujitsu Limited
    Inventors: Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno, Yasunori Abe, Naomi Bizen, Terunobu Maruyama, Yoshiyuki Kato, Tomoyuki Isomura, Hiroshi Ikeda, Miki Takagi
  • Patent number: 6223328
    Abstract: The invention concerns a technique of a wiring processing method used in designing, for example, a large scale integrated circuit.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: April 24, 2001
    Assignee: Fujitsu, Limited
    Inventors: Noriyuki Ito, Tomoyuki Isomura, Hiroshi Ikeda, Toshihiko Tada
  • Patent number: 6146776
    Abstract: A GMR head comprising a spin valve GMR film, which has a free layer containing a Co containing magnetic layer, and a hard magnetic biasing film for inputting a bias magnetic field to the spin valve GMR film. The hard magnetic biasing film is constituted of a film formed by laminating a hard magnetic layer on the magnetic under layer. The hard magnetic layer is disposed adjoining to edge portion of the spin valve GMR film through the magnetic under layer. The magnetic under layer has saturation magnetization Ms.sup.under which satisfies at least one condition of Ms.sup.under .gtoreq.Ms.sup.free and Ms.sup.under .gtoreq.Ms.sup.hard when saturation magnetization of the free layer is Ms.sup.free and saturation magnetization of the hard magnetic layer is Ms.sup.hard. In a MR head of this abutted junction structure, even when the track width is narrowed, occurrence of Barkhausen noise can be effectively suppressed.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: November 14, 2000
    Assignees: Kabushiki Kaisha Toshiba, TDK Corporation
    Inventors: Hideaki Fukuzawa, Yuzo Kamiguchi, Naoyuki Inoue, Hitoshi Iwasaki, Noriyuki Ito, Taro Oike, Hiroaki Kawashima
  • Patent number: 5998016
    Abstract: A spin valve effect MR sensor includes a spin valve effect multi-layered structure. This structure has a first thin film layer of ferromagnetic material with one and the other surfaces, a second thin film layer of ferromagnetic material with one and the other surfaces, a thin film spacer layer of nonmagnetic conductive material deposited between the one surfaces of the first and second ferromagnetic material layers, a thin film layer of anti-ferromagnetic material deposited on the other surface of the second ferromagnetic material layer, for pinning the second ferromagnetic material layer, a thin film layer of anti-diffusion material deposited on the other surface of the first ferromagnetic material layer, and a thin film current bypass layer of nonmagnetic conductive material deposited on the thin film anti-diffusion material layer.
    Type: Grant
    Filed: January 13, 1998
    Date of Patent: December 7, 1999
    Assignee: TDK Corporation
    Inventors: Tetsuro Sasaki, Noriyuki Ito
  • Patent number: 5913515
    Abstract: This invention relates to game machine apparatus having a display device and generating a special condition. In one embodiment, a game machine that varies the display content on a display device provided on a panel thereof, and generates a special condition advantageous to a player when a display result matches a predetermined condition, includes a display manager, a control device, and a special condition generating device. The display manager advances a special game and displays a successively-varying game while no pinball driven onto a panel of the game machine enters a special prize-winning port. The control device executes a one unit game from the current state of the proceeding game series and displays an execution result of the one unit game on the display device when a pinball driven onto the panel of the game machine enters the special prize-winning port.
    Type: Grant
    Filed: October 10, 1997
    Date of Patent: June 22, 1999
    Assignee: Kabushiki Kaisha Ace Denken
    Inventors: Takatoshi Takemoto, Noriyuki Ito
  • Patent number: 5889677
    Abstract: A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno, Yasunori Abe, Naomi Bizen, Terunobu Maruyama, Yoshiyuki Kato, Tomoyuki Isomura, Hiroshi Ikeda, Miki Takagi
  • Patent number: 5889682
    Abstract: A clock routing design method enables a routing design for each hierarchy while paying an attention to each layout hierarchy to which a branch of a clock signal system extends and considering a whole chip. In the clock routing design method, a clock signal line is routed between a plurality of receiver terminals over a plurality of layout hierarchies while considering an equal-delay branch point yielding equal delays of a clock signal at the receiver terminals, the clock signal line is then routed between the equal-delay branch point positioning between the plural receiver terminals and the driver terminal. The clock routing design method is applicable to a layout design of wire patterns, cell, etc. on LSIs, printed circuit boards and the like.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Masayuki Omura, Noriyuki Ito
  • Patent number: 5787268
    Abstract: The invention provides an interactive circuit designing apparatus wherein a logic design, a layout design and a speed analysis can cooperate with each other in processing. The interactive circuit designing apparatus comprises a logical designing section for logically designing a design object circuit, a layout designing section for performing mounting arrangement of logical components constituting a design object circuit based on a result of the logical design and performing wiring between the logical components, and a speed analysis section for performing a speed analysis based on calculation of a delay for each of paths on the design object circuit in accordance with a result of the layout. The logical designing section, the layout designing section and the speed analysis section are connected to each other so as to cooperate with each other when necessary. The interactive circuit designing apparatus is applied to an apparatus for designing a circuit of an LSI, a printed circuit board or a like element.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: July 28, 1998
    Assignee: Fujitsu Limited
    Inventors: Yaroku Sugiyama, Hiroyuki Sugiyama, Noriyuki Ito, Ryouichi Yamashita, Terunobu Maruyama, Yasunori Abe