Patents by Inventor Ofer Levy

Ofer Levy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170224811
    Abstract: Embodiments described herein relate to combinatorial compositions and uses thereof, for example, as vaccine adjuvant compositions, for enhancing immune response, for inducing differentiation of nave T cells to differentiate into IFN-?-producing T cells, and for preventing and treating infections. The combinatorial composition comprises TLR and CLR agonists. The combinatorial composition comprises at least one TLR4 agonist and at least one Dectin-1 agonist, wherein the at least TLR4 agonist is monophosphoryl lipid A (MPLA) or glycopyranosyl lipid A (GLA), or the combinatorial composition comprises at least one TLR7/8 agonist and at least one Mincle agonist.
    Type: Application
    Filed: April 17, 2015
    Publication date: August 10, 2017
    Applicant: CHILDREN'S MEDICAL CENTER CORPORATION
    Inventors: Simon D. Van Haren, Ofer Levy
  • Patent number: 9716646
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: July 25, 2017
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Beeman C. Strong, Ofer Levy, Gabi Malka, Zeev Sperber
  • Patent number: 9696997
    Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Zeev Sperber, Jason W. Brandt
  • Patent number: 9690588
    Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Ahmad Yasin, Michael W. Chynoweth, Ofer Levy, Jason W. Brandt, Angela Schmid
  • Publication number: 20170149554
    Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.
    Type: Application
    Filed: November 24, 2015
    Publication date: May 25, 2017
    Applicant: Intel Corporation
    Inventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
  • Patent number: 9660799
    Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
  • Publication number: 20170107284
    Abstract: This invention relates to a novel target for production of immune and non-immune based therapeutics and for disease diagnosis. More particularly, the invention provides therapeutic antibodies against KRTCAP3, FAM26F, MGC52498, FAM70A or TMEM154 antigens, which are differentially expressed in cancer, and diagnostic and therapeutic usages. This invention further relates to extracellular domains of KRTCAP3, FAM26F, MGC52498, FAM70A and TMEM154 proteins and variants, and therapeutic usages thereof.
    Type: Application
    Filed: November 29, 2016
    Publication date: April 20, 2017
    Inventors: Amir TOPORIK, Amit NOVIK, Anat COHEN-DAYAG, Avi Yeshah ROSENBERG, Eve MONTIA, Galit ROTMAN, Liat DASSA, Merav BEIMAN, Ofer LEVY, Shira WALACH, Shirley SAMEACH- GREENWALD, Yaron KINAR, Zurit LEVINE, Gad S. COJOCARU, Sergey NEMZER
  • Patent number: 9626274
    Abstract: A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Ahmad Yasin, Rajshree A. Chabukswar, Ofer Levy, Michael W. Chynoweth, Charlie J. Hewett
  • Patent number: 9612938
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Frank Binns, Matthew C. Merten, Mayank Bomb, Beeman C. Strong, Peter Lachner, Jason W. Brandt, Itamar Kazachinsky, Ofer Levy, Md A. Rahman
  • Publication number: 20170088607
    Abstract: The present invention is directed to PVRIG polypeptides and their uses.
    Type: Application
    Filed: February 19, 2016
    Publication date: March 30, 2017
    Inventors: Mark White, Sandeep Kumar, Christopher Chan, Spencer Liang, Lance Stapleton, Andrew W. Drake, Yosi Gozlan, Ilan Vaknin, Shirley Sameah-Greenwald, Liat Dassa, Zohar Tiran, Gad. S. Cojocaru, Amir Toporik, Yossef Kliger, Ofer Levy, Arthur Machlenkin, Sergey Nemzer, Yair Benita, Amit Novik
  • Publication number: 20170065676
    Abstract: Described herein is a method of mitigating, in a subject (individual), tissue injury resulting from exposure to radiation (accidental/unintentional or intentional, such as therapeutic), chemoradiotherapy, disease, toxin, or drug or biologic mediated therapy.
    Type: Application
    Filed: June 1, 2016
    Publication date: March 9, 2017
    Applicants: Dana-Farber Cancer Institute, Inc., Children's Medical Center Corporation
    Inventors: Eva Guinan, Ofer Levy
  • Publication number: 20170056471
    Abstract: Described herein is a method of mitigating, in a subject (individual), tissue injury resulting from exposure to radiation (accidental/unintentional or intentional, such as therapeutic), chemoradiotherapy, disease, toxin, or drug or biologic mediated therapy.
    Type: Application
    Filed: June 1, 2016
    Publication date: March 2, 2017
    Applicants: Dana-Farber Cancer Institute, Inc., Children's Medical Center Corporation
    Inventors: Eva Guinan, Ofer Levy
  • Patent number: 9575766
    Abstract: Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: February 21, 2017
    Assignee: Intel Corporation
    Inventors: Ahmad Yasin, Peggy J. Irelan, Ofer Levy, Emile Ziedan, Grant Zhou
  • Publication number: 20170037141
    Abstract: This invention relates to a novel target for production of immune and non-immune based therapeutics and for disease diagnosis. More particularly, the invention provides therapeutic antibodies against VSIG1, ILDR1, LOC253012, AI216611, C1ORF32 or FXYD3 antigens, which are predicted co-stimulatory family members and which are differentially expressed in cancers including, lung cancer, ovarian cancer, and colon cancer, and diagnostic and therapeutic usages. The use of these antibodies for modulating B7 costimulation and related therapies such as the treatment of autoimmunity are also provided. This invention further relates to the discovery of extracellular domains of VSIG1 and its variants, FXYD3 and its variants, ILDR1 and its variants, LOC253012 and its variants, AI216611 and its variants, and C1ORF32 and its variants awhich are suitable targets for immunotherapy, cancer therapy, and drug development.
    Type: Application
    Filed: January 30, 2016
    Publication date: February 9, 2017
    Inventors: Anat COHEN-DAYAG, Merav BEIMAN, Liat DASSA, Marina BUBIS, Shirley SAMEACH- GREENWALD, Dalit LANDESMAN-MILO, Cynthia KOIFMAN, Ofer LEVY, Sergey NEMZER, Tania PERGAM, Yaron KINAR, Zurit LEVINE, Avi ROSENBERG, Galit ROTMAN, Eve MONTIA, Amit NOVIK, Amir TOPORIK, Shira WALACH
  • Patent number: 9538852
    Abstract: Stabilizing apparatus for inclined legs comprises a thigh engageable portion extending generally transversally along the width of the lap of a subject with which the apparatus is bodily engaged, two spaced appendage portions extending downwardly from the thigh engageable portion, a foot engageable portion positionable on an underlying surface, and a portion, such a connecting element and tensioning device, extending from each of the two appendage portions to a foot engageable portion. The two appendage portions are positionable to be substantially in contact with the lateral side of a thigh of the subject. A loop is defined such that each of the portions extending from an appendage portion to a foot engageable portion is suitably tensioned so as to apply forces to a foot engageable portion for resisting a forward foot sliding motion and to an appendage portion for resisting relative transversal motion of an inclined leg.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: January 10, 2017
    Inventors: Ofer Levy, Uri Wolf
  • Publication number: 20160347814
    Abstract: This invention relates to VSTM5 proteins, soluble molecules and fusions thereof which are suitable targets for drug development and for treatment of immune related disorders, immunotherapy, treatment of cancer, infectious disorders and/or sepsis.
    Type: Application
    Filed: March 10, 2016
    Publication date: December 1, 2016
    Inventors: Zurit LEVINE, Galit ROTMAN, Liat DASSA, Ofer LEVY, Gad S. COJOCARU, Amir TOPORIK, Yossef KLIGER, Ilan VAKNIN, Iris HECHT
  • Publication number: 20160272707
    Abstract: The present invention relates to VSTM5-specific antibodies, antibody fragments, and VSTM5 polypeptides, conjugates and compositions comprising same, for modulating (antagonizing or agonizing) one or more of the effects of VSTM5 expression on immunity. More specifically, the present invention relates to VSTM5-specific antibodies, antibody fragments, and VSTM5 polypeptides, conjugates and compositions comprising same for treating and aiding in the diagnosis of cancer, infectious diseases and immune related diseases, e.g., those associated with aberrant (higher or lower than normal) VSTM5 expression by diseased and/or immune cells and/or aberrant (increased or reduced) VSTM5-mediated effects on immunity.
    Type: Application
    Filed: September 11, 2014
    Publication date: September 22, 2016
    Inventors: Zurit LEVINE, Galit ROTMAN, Liat DASSA, Ofer LEVY, Gad S. COJOCARU, Amir TOPORIK, Yossef KLIGER, Andrew POW, Spencer LIANG
  • Publication number: 20160259646
    Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.
    Type: Application
    Filed: May 16, 2016
    Publication date: September 8, 2016
    Inventors: Ahmad Yasin, Michael W. Chynoweth, Ofer Levy, Jason W. Brandt, Angela Schmid
  • Patent number: 9375466
    Abstract: This invention relates to a novel target for production of immune and non-immune based therapeutics and for disease diagnosis. More particularly, the invention provides therapeutic antibodies against VSIG1, ILDR1, LOC253012, AI216611, C1ORF32 or FXYD3 antigens, which are predicted co-stimulatory family members and which are differentially expressed in cancers including, lung cancer, ovarian cancer, and colon cancer, and diagnostic and therapeutic usages. The use of these antibodies for modulating B7 costimulation and related therapies such as the treatment of autoimmunity are also provided. This invention further relates to the discovery of extracellular domains of VSIG1 and its variants, FXYD3 and its variants, ILDR1 and its variants, LOC253012 and its variants, AI216611 and its variants, and C1ORF32 and its variants awhich are suitable targets for immunotherapy, cancer therapy, and drug development.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: June 28, 2016
    Assignee: COMPUGEN LTD
    Inventors: Anat Cohen-Dayag, Merav Beiman, Liat Dassa, Marina Bubis, Shirley Sameach- Greenwald, Dalit Landesman-Milo, Cynthia Koifman, Ofer Levy, Sergey Nemzer, Tania Pergam, Yaron Kinar, Zurit Levine, Avi Rosenberg, Galit Rotman, Eve Montia, Amit Novik, Amir Toporik, Shira Walach
  • Publication number: 20160180079
    Abstract: A method comprises filtering branch trap events at a branch event filter, monitoring a branch event filter to capture indirect branch trap events that cause a control flow trap exception, receiving the indirect branch trap events at a handler and the handler processing the indirect branch trap events
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Ravi L. Sahita, Xiaoning Li, Barry E. Huntley, Ofer Levy, Vedvyas Shanbhogue, Yuriy Bulygin, Ido Ouziel, Michael Lemay, John M. Esper