Abstract: The invention relates to field of connected sport and specifically a method for quantifying sporting activity implemented by a communication system including: a proximity beacon associated with sports equipment, measuring equipment and a communication node, the method including: (a) communicating between the measuring equipment and the beacon in order to recover a first data packet comprising an identifier relating to a sporting activity associated with the sports equipment; (b) transmitting, to the node, a second data packet comprising the identifier; (c) at the node, determining parameterisation data of the measuring equipment according to the identifier; (d) transmitting, to the measuring equipment, a third data packet 230 comprising said parameterisation data; and (e) at the parameterised measuring equipment, quantifying the sporting activity.

Abstract: The invention relates to field of connected sport and specifically a method for quantifying sporting activity implemented by a communication system including: a proximity beacon associated with sports equipment, measuring equipment and a communication node, the method including: (a) communicating between the measuring equipment and the beacon in order to recover a first data packet comprising an identifier relating to a sporting activity associated with the sports equipment; (b) transmitting, to the node, a second data packet comprising the identifier; (c) at the node, determining parameterisation data of the measuring equipment according to the identifier; (d) transmitting, to the measuring equipment, a third data packet 230 comprising said parameterisation data; and (e) at the parameterised measuring equipment, quantifying the sporting activity.

Abstract: The invention relates to a resistive memory (5) including resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device (14) for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device including a first circuit capable of applying an increasing voltage across the selected resistive element while the selected resistive element is at the high value or at the low value, a second circuit capable of detecting the switching of the resistance of the selected resistive element, and a third circuit capable of interrupting the current flowing through the selected resistive element on detection of the switching.

Abstract: The present invention relates to the fields of medicine and cancer treatment. The invention more specifically relates to the use of a panicein or a derivative thereof, to decrease or inhibit, in vitro or ex vivo, the Patched receptor drug efflux activity, in particular the chemotherapeutic drug efflux activity and chemotherapy resistance. The present disclosure further relates to uses of such compounds, in particular to prepare a pharmaceutical composition to allow or improve the efficiency of a therapy of cancer in a subject in need thereof. The compound of the invention can indeed be advantageously used, in combination with at least one chemotherapeutic drug, for treating cancer, for preventing cancer metastasis and/or for preventing cancer recurrence in a subject.

Abstract: The present invention relates to the fields of medicine and cancer treatment. The invention more specifically relates to the use of a panicein or a derivative thereof, to decrease or inhibit, in vitro or ex vivo, the Patched receptor drug efflux activity, in particular the chemotherapeutic drug efflux activity and chemotherapy resistance. The present disclosure further relates to uses of such compounds, in particular to prepare a pharmaceutical composition to allow or improve the efficiency of a therapy of cancer in a subject in need thereof. The compound of the invention can indeed be advantageously used, in combination with at least one chemotherapeutic drug, for treating cancer, for preventing cancer metastasis and/or for preventing cancer recurrence in a subject.

Abstract: The invention more particularly relates to a resistive memory cell comprising a first and a second metal electrodes and a solid electrolyte positioned between the first and the second metal electrodes, with the solid electrolyte comprising a commutation layer in contact with the first electrode and a dielectric layer, with said resistive memory cell being able to be electrically modified so as to switch from a first resistive state to a second resistive state (state LRS) wherein the resistance (RON) of the memory cell is at least ten times smaller than the resistance (ROFF) of the memory cell in the HRS state, in the LRS state the first electrode being so arranged as to supply metal ions intended to form at least a conductive filament through said commutation layer, with the cell being characterized in that, in the LRS state, the memory cell is conductive for a range of voltages between 0 Volts and VREST 2 .

Abstract: The present invention relates to the fields of medicine and cancer treatment. The invention more specifically relates to the use of a panicein or a derivative thereof, to decrease or inhibit, in vitro or ex vivo, the Patched receptor drug efflux activity, in particular the chemotherapeutic drug efflux activity and chemotherapy resistance. The present disclosure further relates to uses of such compounds, in particular to prepare a pharmaceutical composition to allow or improve the efficiency of a therapy of cancer in a subject in need thereof. The compound of the invention can indeed be advantageously used, in combination with at least one chemotherapeutic drug, for treating cancer, for preventing cancer metastasis and/or for preventing cancer recurrence in a subject.

Abstract: Memory cell of the SRAM type, including storage transistors forming a memory point for storing a bit and a read port having at least one MOS transistor, a TFET transistor, a power terminal and a read bit line whereof a potential is designed to vary depending on the value of the stored bit, and such that: the gate of the MOS transistor is connected to the memory point, and the gate of the TFET transistor is able to receive a read command signal; a first electrode of the MOS transistor is connected to the power supply terminal; a second electrode of the MOS transistor is connected to a first electrode of the TFET transistor; a second electrode of the TFET transistor is connected to the read bit line.

Abstract: A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.

Abstract: A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.

Abstract: Memory cell of the SRAM type, including storage transistors forming a memory point for storing a bit and a read port having at least one MOS transistor, a TFET transistor, a power terminal and a read bit line whereof a potential is designed to vary depending on value of the stored bit, and such that: the gate of the MOS transistor is connected to the memory point, and the gate of the TFET transistor is able to receive a read command signal; a first electrode of the MOS transistor is connected to the power supply terminal; a second electrode of the MOS transistor is connected to a first electrode of the TFET transistor; a second electrode of the TFET transistor is connected to the read bit line.

Abstract: A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns.

Abstract: A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.

Abstract: The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (RLRS), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.

Abstract: Provided is a method for preparing nanocapsules having a liquid lipid core and a solid shell and charged in their lipid core with at least one hydrophilic active agent involving combining microemulsions where the active agent remains in the hydrophilic phase of a first microemulsion and chill-hardening the mixture to obtain the nanocapsules charged with the hydrophilic active agent. The nanocapsules comprise the lipid core which is liquid at room temperature and the nanocapsules are encapsulated in a film which is solid at room temperature.

Abstract: A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns.

Abstract: The invention relates to a resistive memory (5) including resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device (14) for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device including a first circuit capable of applying an increasing voltage across the selected resistive element while the selected resistive element is at the high value or at the low value, a second circuit capable of detecting the switching of the resistance of the selected resistive element, and a third circuit capable of interrupting the current flowing through the selected resistive element on detection of the switching.

Abstract: The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (RLRS), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.

Abstract: A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.

Abstract: An integrated circuit on a semiconductor substrate has logic gates comprising FDSOI-type transistors made on said substrate, including at least one first transistor comprising a gate with a first work function, and including a transistor comprising a second work function, a memory including memory cells, each memory cell comprising FDSOI type transistors, including at least one third nMOS transistor with a gate presenting a third work function, the third transistor comprising a buried insulating layer and a ground plane at least one fourth pMOS transistor with a gate presenting said third work function, the fourth transistor comprising a buried insulating layer and a ground plane, the ground planes of the third and fourth transistors being made in a same well separating these ground planes from said substrate.