Abstract: A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.

Abstract: A random access memory cell including: two double-gate access transistors respectively arranged between a first bit line and a first storage node and between a second bit line and a second storage node, a word line, a first double-gate load transistor and a second double-gate load transistor, a first double-gate driver transistor and a second double-gate driver transistor, a mechanism to apply a given potential to at least one electrode of each of the load or driver transistors, and a mechanism to cause the given potential to vary.

Abstract: A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.

Abstract: A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k?1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.

Abstract: A microelectronic device, including at least one transistor including: on a substrate, a semiconductor zone with a channel zone covered with a gate dielectric zone, a mobile gate, suspended above the gate dielectric zone and separated from the gate dielectric zone by an empty space, which the gate is located at an adjustable distance from the gate dielectric zone, and a piezoelectric actuation device including a stack formed by at least one layer of piezoelectric material resting on a first biasing electrode, and a second biasing electrode resting on the piezoelectric material layer, wherein the gate is attached to the first biasing electrode and is in contact with the first biasing electrode, and the piezoelectric actuation device is configured to move the gate with respect to the channel zone.

Abstract: A random access memory microelectronic device, comprising a plurality of cells comprising respectively: a plurality of transistors forming a bistable, a first storage node and a second storage node, a first double gate access transistor to the first storage node and a second double gate access transistor to the second storage node, a first gate of the first access transistor and a first gate of the second access transistor being linked to a first word line, a second gate of the first access transistor and a second gate of the second access transistor being linked to a second word line, the device being moreover equipped: with a reference memory cell provided to deliver a bias potential intended to be applied to one of the respective word lines of one or several given cells of said plurality of cells during reading access of said given cells.

Abstract: The present application relates to a non-volatile random-access memory cell equipped with a suspended mobile gate and with piezoelectric means for operating the gate.

Abstract: A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted.

Abstract: The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and of having, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active circuit is controlled by a gate reverse overbias in the following manner: a voltage step-up charge pump generates a gate bias voltage from pulses delivered by an oscillator having its frequency controlled by a current. The control current Ic is the leakage current of a transistor having technological characteristics similar to those of the power transistor. The system optimizes the current consumption in standby mode, the frequency of the oscillator being reduced when the gate is biased so as to minimize the leakage current. The invention is applicable to circuits powered by a battery or a cell (mobile telephones, cameras, portable computers, etc.).

Abstract: A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate.

Abstract: A microelectronic device comprising: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor comprising a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by means of an insulating zone, said insulating zone having, in a first region between said gate of said first transistor and said channel of said second transistor, a composition and thickness provided so as to enable a coupling between the gate electrode of the first transistor and the channel of the second transistor, said insulating zone comprising a second region around the first region, between the access zones of the first and the second transistor of thickness and composition different to those of said first region.

Abstract: A circuit for biasing the bulk of a MOS transistor, including a capacitive element connecting the bulk of the MOS transistor to a source of an voltage.

Abstract: The present invention relates to a method for preparing particles, notably particles encapsulating an active substance. It also relates to particles obtainable by this process, dispersion thereof, and their use as a vehicle for pharmaceutical, cosmetic, diagnostic, veterinary, phytosanitary active substances or processed foodstuff.

Abstract: This invention relates to an improved microelectronic RAM memory device, provided with 4T or 6T cells made using the double gate technology and each associated with two word lines.

Abstract: A random access memory microelectronic device, comprising a plurality of cells comprising respectively: a plurality of transistors forming a bistable, a first storage node and a second storage node, a first double gate access transistor to the first storage node and a second double gate access transistor to the second storage node, a first gate of the first access transistor and a first gate of the second access transistor being linked to a first word line, a second gate of the first access transistor and a second gate of the second access transistor being linked to a second word line, the device being moreover equipped: with a reference memory cell provided to deliver a bias potential intended to be applied to one of the respective word lines of one or several given cells of said plurality of cells during reading access of said given cells.

Abstract: The present application relates to a non-volatile random-access memory cell equipped with a suspended mobile gate and with piezoelectric means for operating the gate.

Abstract: A transistor device with a mobile suspended gate, the device comprising means for piezoelectric actuation of the gate, and a method for producing such a device.

Abstract: The invention relates to the use of lipids as formulation agents for increasing the bioavailability of protein active ingredients in subcutaneous or intramuscular injectable formulations.

Abstract: The invention concerns a random access memory cell comprising: at least one first plurality of symmetrical dual-gate transistors (TL1T, TL1F, TD1T, TD1F, TL2T, TL2F) forming a flip-flop, at least a first asymmetric dual-gate access transistor (TA1T, TAW1T) and at least a second asymmetric dual-gate access transistor (TA1F, TAW1F) disposed respectively between a first bit line (BLT, WBLT) and a first storage node (T), and between a second bit line (BLF, WBLF) and a second storage node (F), a first gate of the first access transistor (TA1T, TAW1T) and a first gate of the second access transistor (TA1F, TAW1F) being connected to a first word line (WL, WWL) able to route a biasing signal, a second gate (TA1F, TAW1F) of the first access transistor connected to the second storage node (F) and a second gate of the second access transistor connected to the first storage node (T).

Abstract: A circuit for biasing the bulk of a MOS transistor, including a capacitive element connecting the bulk of the MOS transistor to a source of an A.C. voltage.