Abstract: CMOS integrated circuits with very low consumption when idle, and notably the SRAM volatile memories, are provided. The inverters of the circuit are made up of an NMOS transistor and a PMOS transistor. A bias circuit applies a first rear bias voltage NBIAS to the wells of the NMOS transistors and a second rear bias voltage PBIAS to the wells of the PMOS transistors. The bias circuit comprises: a detection array made up of many inverters in parallel, having a common output supplying a logic signal whose value depends on the rear bias voltages applied to the array, a circuit for producing incrementation or decrementation pulses, controlled by the output of the detection array, and an integration circuit linked to the pulse-producing circuit, for producing and varying, progressively by increments in response to these pulses, a bias voltage PBIAS and a bias voltage NBIAS.

Abstract: A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.

Abstract: The invention more particularly relates to a resistive memory cell comprising a first and a second metal electrodes and a solid electrolyte positioned between the first and the second metal electrodes, with the solid electrolyte comprising a commutation layer in contact with the first electrode and a dielectric layer, with said resistive memory cell being able to be electrically modified so as to switch from a first resistive state to a second resistive state (state LRS) wherein the resistance (RON) of the memory cell is at least ten times smaller than the resistance (ROFF) of the memory cell in the HRS state, in the LRS state the first electrode being so arranged as to supply metal ions intended to form at least a conductive filament through said commutation layer, with the cell being characterised in that, in the LRS state, the memory cell is conductive for a range of voltages between 0 Volts and VREST 2 .

Abstract: An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.

Abstract: CMOS integrated circuits with very low consumption when idle, and notably the SRAM volatile memories, are provided. The inverters of the circuit are made up of an NMOS transistor and a PMOS transistor. A bias circuit applies a first rear bias voltage NBIAS to the wells of the NMOS transistors and a second rear bias voltage PBIAS to the wells of the PMOS transistors. The bias circuit comprises: a detection array made up of many inverters in parallel, having a common output supplying a logic signal whose value depends on the rear bias voltages applied to the array, a circuit for producing incrementation or decrementation pulses, controlled by the output of the detection array, and an integration circuit linked to the pulse-producing circuit, for producing and varying, progressively by increments in response to these pulses, a bias voltage PBIAS and a bias voltage NBIAS.

Abstract: The invention relates to an integrated circuit including an active semiconducting layer separated from a semiconducting substrate layer by an embedded insulating material surface, including: first and second transistors (205, 213) of a single type; first and second floorplans arranged vertically perpendicular to the first and second transistors; wherein the first transistor has a doping of the floorplan thereof, opposite that of the source thereof, and a first threshold voltage; the second transistor has a doping of the floorplan thereof, identical to that of the source thereof, and a second threshold voltage; the first threshold voltage is dependent on the potential difference applied between the source and the floorplan of the first transistor; and the second threshold voltage is dependent on the potential difference applied between the source and the floorplan of the second transistor.

Abstract: A multi-level integrated circuit, having a superposition of a first stack and a second stack of layers, and including a first row of electronic devices produced in the first stack, extending parallel to a first direction and fitting into a first volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H1; a second row of electronic devices produced in the second stack, extending parallel to the first direction and fitting into a second volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H2<H1; and a plurality of electrical connection elements passing through the second stack of layers, each connection element fitting into a third volume arranged on the first volume and next to the second volume.

Abstract: An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.

Abstract: A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and second portions is separated from the support substrate by an electrically insulating material. The electrically insulating material is different from the material forming the support substrate. The first portion of the semi-conducting area is facing the first counter-electrode. The second portion of the semi-conducting area is facing the second counter-electrode.

Abstract: A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k?1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.

Abstract: A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.

Abstract: A method for making a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least one first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of the double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively; and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least a first implantation selective relative to the first block, the implantation being done on a first side of the given structure, the part of the structure on the other side of the normal to the principal plane of the substrate passing through the semiconducting zone not being implanted.

Abstract: An integrated circuit on a semiconductor substrate has logic gates comprising FDSOI-type transistors made on said substrate, including at least one first transistor comprising a gate with a first work function, and including a transistor comprising a second work function, a memory including memory cells, each memory cell comprising FDSOI type transistors, including at least one third nMOS transistor with a gate presenting a third work function, the third transistor comprising a buried insulating layer and a ground plane at least one fourth pMOS transistor with a gate presenting said third work function, the fourth transistor comprising a buried insulating layer and a ground plane, the ground planes of the third and fourth transistors being made in a same well separating these ground planes from said substrate.

Abstract: An etching mask, comprising the delineation pattern of the gate electrode, of a source contact, a drain contact and a counter-electrode contact, is formed on a substrate of semi-conductor on insulator type. The substrate is covered by a layer of dielectric material and a gate material. The counter-electrode contact is located in the pattern of the gate electrode. The gate material is etched to define the gate electrode, the source contact and drain contacts and the counter-electrode contact. A part of the support substrate is released through the pattern of the counter-electrode contact area. An electrically conductive material is deposited on the free part of the support substrate to form the counter-electrode contact.

Abstract: The present invention relates to a method for preparing particles, notably particles encapsulating an active substance. It also relates to particles obtainable by this process, dispersion thereof, and their use as a vehicle for pharmaceutical, cosmetic, diagnostic, veterinary, phytosanitary active substances or processed foodstuff.

Abstract: A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate.

Abstract: A random access memory cell including: two double-gate access transistors respectively arranged between a first bit line and a first storage node and between a second bit line and a second storage node, a word line, a first double-gate load transistor and a second double-gate load transistor, a first double-gate driver transistor and a second double-gate driver transistor, a mechanism to apply a given potential to at least one electrode of each of the load or driver transistors, and a mechanism to cause the given potential to vary.

Abstract: The memory cell is of SRAM type with four transistors provided with a counter-electrode. It comprises a first area made from semiconductor material with a first transfer transistor and a first driver transistor connected in series, their common terminal defining a first electric node. A second transfer transistor and a second driver transistor are connected in series on a second area made from semiconductor material and their common terminal defines a second electric node. The support substrate comprises first and second counter-electrodes. The first and second counter-electrodes are located respectively facing the first and second semiconductor material areas. The first transfer transistor and second driver transistor are on a first side of a plane passing through the first and second electric nodes whereas the first driver transistor and second transfer transistor are on the other side of the plane.

Abstract: A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.

Abstract: A multi-level integrated circuit comprising a superposition of a first stack and a second stack of layers, and including: a first row of electronic devices produced in the first stack, extending parallel to a first direction and fitting into a first volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H1; a second row of electronic devices produced in the second stack, extending parallel to the first direction and fitting into a second volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H2<H1; a plurality of electrical connection elements passing through the second stack of layers, each connection element fitting into a third volume arranged on the first volume and next to the second volume.