Patents by Inventor On Haran

On Haran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190320341
    Abstract: Apparatus and methods that mitigate interferences between two vehicle-to everything (V2X) communications channels to maintain a sufficient communication range for both channels. A method comprises, in a V2X communication unit, detecting energy of an adjacent channel, or current and future scheduled transmission in the adjacent channel, if available, the adjacent channel being adjacent to a main channel, and if adjacent channel transmission is detected, deferring transmission in the main channel to maintain a sufficient communication range for both the main channel and the adjacent channel.
    Type: Application
    Filed: March 6, 2019
    Publication date: October 17, 2019
    Inventor: ONN HARAN
  • Patent number: 10446550
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Balaji Kannan, Ayse M. Ozbek, Tao Chu, Bala Haran, Vishal Chhabra, Katsunori Onishi, Guowei Xu
  • Patent number: 10423268
    Abstract: A method includes sampling output from sensor having electrode junctions integrated on a device including a display, detecting capacitance between the device ground and a user (CBD) based on the output sampled and a pre-defined model, and defining one of two grounding states of the device based on the capacitance detected. Output is processed based on the grounding state defined and touch coordinates are determined based on the output processed. The touch coordinates are reported to a controller of the display.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 24, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Michael Orlovsky, Amil Winebrand, On Haran
  • Patent number: 10418614
    Abstract: Electrical feedthroughs are presented for redistributing thermally-induced stresses that result from welding. In some embodiments, an electrical feedthrough includes a tubular conduit having a flange at one end. The flange includes a first surface disposed opposite a second surface. The first surface includes at least one of a protrusion and a notch. The electrical feedthrough also includes an electrically-conductive terminal disposed through the tubular conduit. An electrically-insulating material is disposed between the tubular conduit and the electrically-conductive terminal and forms a seal therebetween. The protrusion and the notch are configured individually or as a combination to reduce thermally-induced stresses within the electrically-insulating material that result from welding the flange. Methods for welding such electrical feedthroughs to a wall, such as a wall of a battery housing, are also presented.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 17, 2019
    Assignee: Apple Inc.
    Inventors: Angelo V. Marasco, Haran Balaram
  • Publication number: 20190281437
    Abstract: Apparatuses, systems, and methods broadcast a device state in a wireless communication network. A wireless audio output device is configured to be paired with a second wireless device via a first piconet connection, wherein the second wireless device comprises a source of audio data to be output by the wireless audio output device. The wireless audio output device includes a processor configured to detect a change in the state of the wireless audio output device and set a transmission parameter of a broadcast transmission based at least in part on the detected change in the state and a transceiver configured to broadcast an advertising message to the second wireless device including information describing the wireless audio output device via the broadcast transmission.
    Type: Application
    Filed: May 29, 2019
    Publication date: September 12, 2019
    Inventors: Robert D. Watson, Sriram HARi HARAN, Ganesha Adkasthala Ganapathi BATTA, Jason GILES
  • Publication number: 20190277332
    Abstract: An electrified vehicle assembly includes, among other things, an outer shaft that is rotatable about an axis. The outer shaft rotatably couples a motor of an electrified vehicle to a transmission component of the electrified vehicle. A shaft insert provides a conduit for a fluid and that blocks the fluid from flowing radially between the shaft insert and the outer shaft relative to the axis. The shaft insert includes a polymer-based material, a composite material, or both.
    Type: Application
    Filed: May 29, 2019
    Publication date: September 12, 2019
    Inventors: Cyrille Goldstein, Joel Hetrick, Edward William Haran, Elizabeth Rose Bifano
  • Patent number: 10401616
    Abstract: Disclosed herein is a control circuit for a movable mirror. The control circuit includes driving circuitry configured to drive the movable mirror with a drive signal to effectuate oscillating of the movable mirror, opening angle determination circuitry configured to determine an opening angle of the movable mirror, and amplitude control circuitry. The amplitude control circuitry is configured to a) first cause the driving circuitry to generate the drive signal as having an upper threshold drive amplitude, and b) then later cause the driving circuitry to generate the drive signal as having a nominal drive amplitude, as a function of the opening angle of the movable mirror being equal to a desired opening angle.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics Ltd.
    Inventor: Elik Haran
  • Publication number: 20190267371
    Abstract: One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 29, 2019
    Inventors: Bala Haran, Christopher Sheraw, Mahender Kumar
  • Publication number: 20190258395
    Abstract: Content on a display user interface of an electronic device, such as a wearable electronic device, can be manipulated using capacitive touch sensors that may be seamlessly integrated into the housing or strap of the electronic device. The capacitive touch sensors can advantageously replace mechanical buttons and other mechanical user interface components, such as a crown, to provide industrial design opportunities not possible with the inclusion of mechanical buttons and mechanical interface components. Moreover, the capacitive touch sensors can enable ambidextrous user interface control of content displayed on a touchscreen without requiring the user to touch the touchscreen. In some examples, content displayed on the touchscreen can be accessed in response to a variety of touch gestures processed by the capacitive touch sensors.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Inventor: Haran Balaram
  • Publication number: 20190259656
    Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Inventors: Paul A. NYHUS, Mohit K. HARAN, Charles H. WALLACE, Robert M. BIGWOOD, Deepak S. RAO, Alexander F. KAPLAN
  • Patent number: 10388729
    Abstract: Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John Zhang, Lawrence Clevenger, Kangguo Cheng, Balasubramanian Haran
  • Patent number: 10381458
    Abstract: A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew M. Greene, Balasubramanian P. Haran, Injo Ok, Charan V. Surisetty
  • Patent number: 10382339
    Abstract: A computer network appliance may include a memory and a processor cooperating with the memory to run a classification kernel module performing traffic shaping on data packets based upon a first set of queuing disciplines (qdiscs). The processor may further run at least one virtual device also performing traffic shaping on the data packets based upon a second set of qdiscs different than the first set of qdiscs, and provide the data packets to a network interface.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: August 13, 2019
    Assignee: Citrix Systems, Inc.
    Inventors: Jeffrey Haran, Ashwani Wason, Nicholas Stavrakos, Grisha Kotlyar
  • Publication number: 20190241939
    Abstract: Provided herein, in some embodiments, are systems, methods, compositions, and kits for detecting and quantifying analytes using a primary analyte binding molecule conjugated to a nucleic acid template.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 8, 2019
    Inventor: Sudha Haran
  • Patent number: 10352351
    Abstract: An exemplary shaft assembly includes an outer shaft rotatable about an axis, and a shaft insert that provides a conduit for a fluid and blocks the fluid from flowing radially between the shaft insert and the outer shaft relative to the axis. An exemplary shaft assembling method includes positioning a shaft insert within an outer shaft. The shaft insert has a fluid conduit and is configured to block fluid from communicating radially between the shaft insert and the outer shaft.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 16, 2019
    Assignee: Ford Global Technologies, LLC
    Inventors: Cyrille Goldstein, Joel Hetrick, Edward William Haran, Elizabeth Rose Bifano
  • Patent number: 10355549
    Abstract: A machine for obtaining very high power density is provided, significantly increasing the air-gap magnetic flux density and eliminating the ferromagnetic steel traditionally employed to carry and shield magnetic flux. In one embodiment, an arrangement of main coils and a set of compensating coils is employed to cancel out the field outside the machine without the use of iron while maintaining air gap field levels that are 3 to 10 times greater than conventional machines.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: July 16, 2019
    Inventor: Kiruba Sivasubramaniam Haran
  • Publication number: 20190206728
    Abstract: Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 4, 2019
    Inventors: Charles H. WALLACE, Marvin Y. PAIK, Hyunsoo PARK, Mohit K. HARAN, Alexander F. KAPLAN, Ruth A. BRAIN
  • Patent number: 10324620
    Abstract: Content on a display user interface of an electronic device, such as a wearable electronic device, can be manipulated using capacitive touch sensors that may be seamlessly integrated into the housing or strap of the electronic device. The capacitive touch sensors can advantageously replace mechanical buttons and other mechanical user interface components, such as a crown, to provide industrial design opportunities not possible with the inclusion of mechanical buttons and mechanical interface components. Moreover, the capacitive touch sensors can enable ambidextrous user interface control of content displayed on a touchscreen without requiring the user to touch the touchscreen. In some examples, content displayed on the touchscreen can be accessed in response to a variety of touch gestures processed by the capacitive touch sensors.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: June 18, 2019
    Assignee: APPLE INC.
    Inventor: Haran Balaram
  • Publication number: 20190181042
    Abstract: One illustrative method disclosed includes, among other things, forming at least one layer of sacrificial material above an underlying conductive structure, forming a sacrificial contact structure in the at least one layer of sacrificial material and forming at least one layer of insulating material around the sacrificial contact structure. In this example, the method also includes performing at least one process operation to expose an upper surface of the sacrificial contact structure, removing the sacrificial contact structure so as to form a contact opening that exposes the upper surface of the underlying conductive structure and forming a final contact structure in the contact opening, the final contact structure conductively contacting the underlying conductive structure.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: Ruilong Xie, Lars W. Liebmann, Balasubramanian Pranatharthi Haran, Veeraraghavan Basker
  • Patent number: 10319625
    Abstract: Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Mohit K. Haran, Charles H. Wallace, Robert M. Bigwood, Deepak S. Rao, Alexander F. Kaplan