Abstract: An active stylus includes a stylus tip and a pressure sensor disposed proximate to the stylus tip. A stylus controller is configured to receive, from the pressure sensor, a current pressure value quantifying a pressure measured at the stylus tip. The stylus controller receives, from a separate display device, a proximity indicator that indicates a current estimated proximity of the stylus tip to a surface of a touch-sensitive display of the display device. Based at least on both of (1) the proximity indicator received from the separate display device, and (2) a comparison between the current pressure value and a touch input pressure threshold, the stylus controller sends a touch status indicator to the separate display device.

Abstract: Integrated circuit structures having a dielectric gate wall and a dielectric gate plug, and methods of fabricating integrated circuit structures having a dielectric gate wall and a dielectric gate plug, are described. For example, an integrated circuit structure includes a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate wall is laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate wall on the STI structure. A dielectric gate plug is on the dielectric gate wall.

Abstract: Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.

Abstract: A device for detecting nucleic acids in a biological sample has a sample port, a lysis station and a sample conduit configured to mix a sample and lysis agent to form a sample-lysis mixture, pass the sample-lysis mixture across a solid-state membrane to capture nucleic acids in the biological sample therein, and receive the remainder of the sample-lysis mixture in a waste chamber. The wash station is configured to introduce the wash solution following the sample-lysis mixture, pass the wash solution across the solid-state membrane to purify nucleic acids captured therein, and receive the wash solution from the solid-state membrane in the waste chamber. The elution station is configured to pass the eluent across the solid-state membrane, elute captured nucleic acids from the solid-state membrane, and pass the captured nucleic acids into one or more reaction chambers for amplifying and detecting the captured nucleic acids.

Abstract: A high-efficiency, high specific power electric motor/generator for aircraft use provides a cantilevered external rotor removed from load thrust. and vibration by an isolator and hearing set between the rotor and stator reducing material demands and weight otherwise required for stiffness to preserve close rotor/stator proximity.

Abstract: Techniques are provided herein to form semiconductor devices having a different number of semiconductor nanoribbons compared to other semiconductor devices on the same substrate. In one example, two different semiconductor devices of a given memory cell, such as a random access memory (RAM) cell, include a p-channel device and an n-channel device. More specifically, the p-channel device may be a GAA transistor with a first number of semiconductor nanoribbons while the n-channel device may be a GAA transistor with a second number of semiconductor nanoribbons that is greater than the first number of semiconductor nanoribbons. In some cases, the n-channel device(s) have one additional semiconductor nanoribbon compared to the p-channel device(s). Depending on when the nanoribbons are removed during the fabrication process, different structural outcomes will occur that can be detected in the final device.

Abstract: A control system includes a mirror controller generating horizontal and vertical mirror synchronization signals for a mirror based upon a mirror clock signal. Laser modulation circuitry generates horizontal and vertical laser synchronization signals as a function of first and second laser clock signals and generates control signals for a laser that emits a laser beam that impinges on the mirror. First synchronization circuitry receives the horizontal mirror synchronization signal and the horizontal laser synchronization signal, and modifies generation of the first laser clock signal to achieve alignment between the horizontal mirror synchronization signal and horizontal laser synchronization signal. Second synchronization circuitry receives the vertical mirror synchronization signal and the vertical laser synchronization signal, and modifies generation of the second laser clock signal to achieve alignment between the vertical mirror synchronization signal and vertical laser synchronization signal.

Abstract: A Head-Mounted Display (HMD) is provided which comprises a camera configured to capture a video of a real-world scene with a first field-of-view (FoV), a network interface circuit configured to stream video to a receiving display device, and processing means which is operative to generate a 3D model of the real-world scene, and to generate a video from the 3D model using a second FoV which is wider than the first FoV. The processing means is further operative to estimate a motion of the camera, and to stream the generated video to the receiving display device if the estimated motion of the camera satisfies one or more conditions indicative of rapid motion, else stream the captured video to the receiving display device.

Abstract: An apparatus and method for a voltage driver circuit where a path between a ground node and an output node includes an inductor and/or another storage element and an energy transfer circuit composed of at least two switching elements (e.g., transistors) and at least two valve elements (e.g. diodes). The energy transfer circuit operates to discharge a capacitive load (e.g. output capacitor) into the storage element and facilitate transition from low to high voltage while increasing efficiency. An additional path to ground may be included via another switching element to prevent crosstalk and hold the output at ground potential.

Abstract: The present disclosure relates to a method and an ad decision sever for determining personalized messages during a provisioning of digital content. The method comprises to provide a set of personalized messages candidates by executing a relevance algorithm, which matches message metadata and content metadata. The method continues with receiving calculated network costs for the set of personalized message candidates in order to determine a set of personalized messages, which are optimized with respect to the received network costs by applying a multivariate optimization algorithm.

Abstract: An artificial intelligence (AI) engine assists in the creation of product descriptions. For example, a system that includes the AI engine receives raw data including a description of a product and generates a search query based on the raw data to search the internet for possible product descriptions that satisfy the query. The system can parse the product descriptions into categories of content that map to sections of a template and creating the custom product description based on a selection and combination of the categories of content of the product descriptions matched to sections of the template. An AI-engine is trained based on the selection and combination of the categories of content and ranks the content based on a frequency of being included in custom product descriptions such that the system can later recommend content in accordance with the ranking for creating an optimal custom product.

Abstract: Devices for low distraction operation of a bike rider group and methods for performing same. A device installed in a bike carrying a member of a bike rider group acting as self-rider, may comprise a rider input analyzer module configured to analyze a self-input provided by the self-rider and to provide a data element reflecting the self-input, a radio modem for sending a V2X message that includes the data element reflecting the self-input and for receiving V2X message that includes a data element from a remote member of the bike rider group, an alert analyzer module configured to detect an alert relevant to the self-rider based on the data element reflecting the self-input and on the data element received from the remote member, and a display configured to display the alert relevant to the self-rider with minimal distraction to the self-rider.

Abstract: A method performed by an electronic device for requesting tiles relating to a viewport of an ongoing omnidirectional video stream is provided. The ongoing omnidirectional video stream is provided by a server to be displayed to a user of the electronic device. The electronic device predicts for an impending time period, a future head gaze of the user in relation to a current head gaze of the user, based on: A current head gaze relative to a position of shoulders of the user, a limitation of the head gaze of the user bounded by the shoulders position of the user, and a current eye gaze and eye movements of the user. The electronic device then sends a request to the server. The request requests tiles relating to the viewport for the impending time period, selected based on the predicted future head gaze of the user.

Abstract: Battery systems according to embodiments of the present technology may include a battery including a first electrode terminal and a second electrode terminal accessible along a first surface of the battery. The battery systems may also include a module electrically coupled with the battery. The module may include a first mold extending toward the battery. The first mold may define a recess along a first surface of the first mold proximate the first electrode terminal and the second electrode terminal. The module may include a first conductive tab electrically coupling the module with the first electrode terminal. The first electrode terminal may be at least partially positioned within a space defined by the recess defined by the first mold. The module may also include a second conductive tab electrically coupling the module with the second electrode terminal.

Abstract: An integrated circuit structure comprises a first and second vertical arrangement of horizontal nanowires in a PMOS region and in an NMOS region. A first gate stack having a P-type conductive layer surrounds the first vertical arrangement of horizontal nanowires. A second gate stack surrounds the second vertical arrangement of horizontal nanowires. In one embodiment, the second gate stack has an N-type conductive layer, the P-type conductive layer is over the second gate stack, and an N-type conductive fill is between N-type conductive layer and the P-type conductive layer to provide same polarity metal filled gates. In another embodiment, the second gate stack has an N-type conductive layer comprising Titanium (Ti) and “Nitrogen (N) having a low saturation thickness of 3-3.5 nm surrounding the nanowires, and the N-type conductive layer is covered by the P-type conductive layer.

Abstract: Dummy gate patterning lines, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a first gate line along a first direction. A second gate line is parallel with the first gate line along the first direction. A third gate line extends between and is continuous with the first gate line and the second gate line along a second direction, the second direction orthogonal to the first direction.

Abstract: Back-side transistor contacts that wrap around a portion of source and/or drain semiconductor bodies, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such back-side transistor contacts are coupled to a top and a side of the source and/or drain semiconductor and extend to back-side interconnects. Coupling to top and side surfaces of the source and/or drain semiconductor reduces contact resistance and extending the metallization along the side reduces transistor cell size for improve device density.

Abstract: Integrated circuit structures having plugged metal gates, and methods of fabricating integrated circuit structures having plugged metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on the STI structure. The gate dielectric material layer and the conductive gate layer are along a side of the dielectric gate plug, and the gate dielectric material layer is in direct contact with an entirety of the side of the dielectric gate plug.

Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.

Abstract: Integrated circuit structures having metal gates with reduced aspect ratio cuts, and methods of fabricating integrated circuit structures having metal gates with reduced aspect ratio cuts, are described. For example, an integrated circuit structure includes a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric structure is laterally spaced apart from the plurality of horizontally stacked nanowires. A dielectric gate plug is landed on the dielectric structure.