Patents by Inventor Or Inbar

Or Inbar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230015117
    Abstract: Techniques for tuning an image editing operator for reducing a distractor in raw image data are presented herein. The image editing operator can access the raw image data and a mask. The mask can indicate a region of interest associated with the raw image data. The image editing operator can process the raw image data and the mask to generate processed image data. Additionally, a trained saliency model can process at least the processed image data within the region of interest to generate a saliency map that provides saliency values. Moreover, a saliency loss function can compare the saliency values provided by the saliency map for the processed image data within the region of interest to one or more target saliency values. Subsequently, the one or more parameter values of the image editing operator can be modified based at least in part on the saliency loss function.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 19, 2023
    Inventors: Kfir Aberman, David Edward Jacobs, Kai Jochen Kohlhoff, Michael Rubinstein, Yossi Gandelsman, Junfeng He, Inbar Mosseri, Yael Pritch Knaan
  • Patent number: 11537292
    Abstract: A method and apparatus for enhancing reliability of a data storage device. The storage device controller is configured to convert a typical UBER-type event to an MTBF (FFR) event by converting a data error event into a drive functional failure. In this context, the converted error is not counted as an UBER type event for purposes of determining the reliability of the storage device.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Karin Inbar, Avichay Haim Hodes, Einat Lev
  • Patent number: 11537326
    Abstract: The present disclosure generally relates to efficiently relocating data within a data storage device. By implementing an error correction code (ECC) module in a complementary metal oxide semiconductor (CMOS) chip for each memory die within a memory array of a memory device, the data can be relocated more efficiently. The ECC decodes the codewords at the memory die. The metadata is then extracted from the decoded codewords and transferred to a controller of the data storage device. A flash translation layer (FTL) module at the controller then checks whether the data is valid by comparing the received metadata to FTL tables. If the metadata indicates the data is valid, then the data is relocated.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Uri Peltz, Karin Inbar
  • Publication number: 20220408101
    Abstract: A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Inventors: Alon MARCU, Ofir PELE, Ariel NAVON, Shay BENISTY, Karin INBAR, Judah Gamliel HAHN
  • Publication number: 20220405601
    Abstract: A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Inventors: Alon MARCU, Ariel NAVON, Judah Gamliel HAHN, Shay BENISTY, Eran SHARON, Karin INBAR
  • Publication number: 20220382452
    Abstract: A data storage device includes a non-volatile memory (NVM) device and a controller coupled to the NVM device. The controller is configured to create a bad block table that tracks bad blocks of the NVM device, send the bad block table to a host memory location, and check the bad block table to determine whether a block to be read or written to is bad. The controller is further configured to request information on a bad block from the bad block table located in the host memory location, determine that the requested information is not available from the host memory location, and retrieve the requested information from a location separate from the host memory location. A sum of the times to generate a request to check the flat relink table, execute the request, and retrieve the requested information is less than a time to process a host command.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 1, 2022
    Inventors: Karin INBAR, David HALIVA, Gadi VISHNE
  • Publication number: 20220365679
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
    Type: Application
    Filed: August 1, 2022
    Publication date: November 17, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Karin Inbar
  • Patent number: 11503751
    Abstract: A method, system and paint for suppressing emission of high frequency electromagnetic radiation from an electronic system, the electronic system including at least one power supply unit, at least one printed circuit board (PCB) and at least one integrated circuit are provided. The method includes providing an electrically conductive housing configured to accommodate and encase the electronic system, the housing having an inner conductive surface, and applying a layer of an electromagnetic absorbing paint to the inner conductive surface of the housing to substantially cover the inner surface by the layer, the electromagnetic absorbing paint comprises a liquid matrix and an electromagnetic absorbing material.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: November 15, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Avner Badihi, Pavel Vilner, Inbar Gozlan, Amir Pinhasovich
  • Publication number: 20220353256
    Abstract: Usage-limited passcodes support authentication when onboarding new employees, when recovering access after an enrolled device is lost or temporarily unavailable, or when registering passwordless authentication methods for new devices during an out of the box setup, among other scenarios. Usage-limited passcodes are also referred to as “temporary access passes” or TAPs. TAP usage may be limited to a specific number of uses, particular kinds of uses, certain time periods, or a combination thereof. A TAP includes a code string and an implementation of corresponding tokens, rights, and other identity aspects within an enhanced access control infrastructure. TAP usage may supplement or replace other authentication, and in particular may replace authentication through a username and password combination, thereby enhancing both usability and security. Self-service identity confirmation may be used to obtain a TAP. Redirection to a federated domain identity provider may be avoided during TAP authentication.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Inventors: Inbar CIZER KOBRINSKY, Anirban BASU, Ananda SINHA, Sarat SUBRAMANIAM, Alexander T. WEINERT, Nitika GUPTA, Kamen MOUTAFOV, Ashok CHANDRASEKARAN
  • Publication number: 20220349935
    Abstract: A semiconductor integrated circuit (IC) comprising a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I/O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad. A circuit in the IC, or a computer in communication with the IC, determines electrical connection integrity of the pad based on the measured delay of the I/O buffer.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Eyal FAYNEH, Shai COHEN, Evelyn LANDMAN, Yahel DAVID, Inbar WEINTROB
  • Publication number: 20220343048
    Abstract: Determining one or more device parameters (Dp) of one or more parts of an integrated circuit (IC), including: simulating the IC; measuring one or more electrical characteristics of the one or more parts of the IC; using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to determine the one or more device parameters (Dp) of the one or more parts of the IC; for each part of the IC, determining a corresponding joint probability distribution of the one or more device parameters using the simulation; using maximum likelihood (ML) techniques to determine an estimate of the one or more device parameters; and using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to improve the estimate of the one or more device parameters.
    Type: Application
    Filed: May 13, 2020
    Publication date: October 27, 2022
    Inventors: Eyal FAYNEH, Guy REDLER, Yahel DAVID, Inbar WEINTROB, Evelyn LANDMAN
  • Publication number: 20220343103
    Abstract: An approach to identifying text within an image may be presented. The approach can receive an image. The approach can classify an image on a pixel-by-pixel basis whether the pixel is text. The approach can generate bounding boxes around groups of pixels that are classified as text. The approach can mask sections of an image that where pixels are not classified as text. The approach may be used as a pre-processing technique for optical character recognition in documents, scanned images, or still images.
    Type: Application
    Filed: April 27, 2021
    Publication date: October 27, 2022
    Inventors: Udi Barzelay, Ophir Azulai, Inbar Shapira
  • Patent number: 11456005
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for audio-visual speech separation. A method includes: obtaining, for each frame in a stream of frames from a video in which faces of one or more speakers have been detected, a respective per-frame face embedding of the face of each speaker; processing, for each speaker, the per-frame face embeddings of the face of the speaker to generate visual features for the face of the speaker; obtaining a spectrogram of an audio soundtrack for the video; processing the spectrogram to generate an audio embedding for the audio soundtrack; combining the visual features for the one or more speakers and the audio embedding for the audio soundtrack to generate an audio-visual embedding for the video; determining a respective spectrogram mask for each of the one or more speakers; and determining a respective isolated speech spectrogram for each speaker.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 27, 2022
    Assignee: Google LLC
    Inventors: Inbar Mosseri, Michael Rubinstein, Ariel Ephrat, William Freeman, Oran Lang, Kevin William Wilson, Tali Dekel, Avinatan Hassidim
  • Publication number: 20220280761
    Abstract: Various systems and methods are provided for reducing pressure at an outflow of a duct, such as the thoracic duct or the lymphatic duct, for example, the right lymphatic duct. A catheter system can be configured to be at least partially implanted within a vein of a patient in the vicinity of an outflow port of a duct of the lymphatic system. The catheter system includes first and second selectively deployable restriction members each configured to be activated to at least partially occlude the vein within which the catheter is implanted and to thus restrict fluid within a portion of the vein. The catheter system includes an impeller configured to be driven by a motor to induce a low pressure zone between the restriction members by causing blood to be pumped through the catheter when the restriction members occlude the vein.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Yaacov Nitzan, Sagi Raz, Shani Chen, Or Inbar
  • Publication number: 20220280762
    Abstract: Various systems and methods are provided for reducing pressure at an outflow of a duct, such as the thoracic duct or the lymphatic duct, for example, the right lymphatic duct. A catheter system can be configured to be at least partially implanted within a vein of a patient in the vicinity of an outflow port of a duct of the lymphatic system. The catheter system includes first and second selectively deployable restriction members each configured to be activated to at least partially occlude the vein within which the catheter is implanted and to thus restrict fluid within a portion of the vein. The catheter system includes an impeller configured to be driven by a motor to induce a low pressure zone between the restriction members by causing blood to be pumped through the catheter when the restriction members occlude the vein.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Yaacov Nitzan, Sagi Raz, Shani Chen, Or Inbar
  • Publication number: 20220282195
    Abstract: A mobile processing laboratory (MPL) is provided, configured for facilitating performing therewithin a cell therapy process. The MPL comprises a portable enclosure; one or more pieces of laboratory equipment for carrying out the cell therapy process and being housed within the enclosure; a plurality of sensors, each configured to measure information regarding the environment, cellular material of the process, and/or one of the pieces of laboratory equipment; and a computer system configured for management of the cell therapy process. The computer system is configured to facilitate collecting data from the sensors, and to optimize one or more activities associated with performance of the cell therapy process based on data collected from one or more other MPLs configured for performing therewithin substantially the same cell therapy process.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 8, 2022
    Applicant: ORGENESIS INC,
    Inventors: Gilad Ish Shalom, Inbar Barzilay, Vered Caplan
  • Patent number: 11436133
    Abstract: Example implementations relate to comparable UI object identifications. Some implementations may include a data capture engine to capture data points during test executions of the application under test. The data points may include, for example, test action data and application action data. Additionally, some implementations may include a data correlation engine to correlate each of the data points with a particular test execution of the test executions, and each of the data points may be correlated based on a sequence of events that occurred during the particular test execution. Furthermore, some implementations may also automatically identify, based on the correlated data points, a set of comparable UI objects.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: September 6, 2022
    Assignee: Micro Focus LLC
    Inventors: Inbar Shani, Ilan Shufer, Amichai Nitsan
  • Patent number: 11435920
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Karin Inbar
  • Publication number: 20220268644
    Abstract: A semiconductor integrated circuit (IC) comprising: a first ring oscillator (ROSC) circuit and a second ROSC circuit at spaced apart locations in the IC, each ROSC circuit having a respective oscillation frequency in operation that varies with temperature; a semiconductor temperature sensor, located in the IC proximate to the first ROSC circuit and providing a sensor output signal indicative of temperature; and at least one processor, configured to indicate a temperature at the second ROSC circuit based at least on: the sensor output signal, the oscillation frequency of the second ROSC circuit, and the oscillation frequency of the first ROSC circuit.
    Type: Application
    Filed: July 29, 2020
    Publication date: August 25, 2022
    Inventors: Eyal FAYNEH, Guy REDLER, Evelyn LANDMAN, Inbar WEINTROB, Yahel DAVID, Faten TANASRA
  • Publication number: 20220260630
    Abstract: An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.
    Type: Application
    Filed: March 24, 2022
    Publication date: August 18, 2022
    Inventors: Eyal FAYNEH, Edi SHMUELI, Alexander BURLAK, Evelyn LANDMAN, Inbar WEINTROB, Yahel DAVID, Shai COHEN, Guy REDLER