Abstract: A noise reduction device is configured by use of: means for calculating a predetermined constant, and a predetermined reference signal R?(T) in the frequency domain, respectively by use of adaptive coefficients W?(m), and for thereby obtaining estimated values N? and Q?(T) respectively of stationary noise components, and non-stationary noise components corresponding to the reference signal, which are included in a predetermined observed signal X?(T) in the frequency domain; means and for applying a noise reduction process to the observed signal on the basis of each of the estimated values, and for updating each of the adaptive coefficients on the basis of a result of the process; and an adaptive learning means and for repeating the obtaining of the estimated values and the updating of the adaptive coefficients, and for thereby learning each of the adaptive coefficients.

Abstract: The present invention relates to a method, preprocessor, speech recognition system, and program product for extracting a target speech by removing noise. In an embodiment of the invention target speech is extracted from two input speeches, which are obtained through at least two speech input devices installed in different places in a space, applies a spectrum subtraction process by using a noise power spectrum (U?) estimated by one or both of the two speech input devices (X?(T)) and an arbitrary subtraction constant (?) to obtain a resultant subtracted power spectrum (Y?(T)). The invention further applies a gain control based on the two speech input devices to the resultant subtracted power spectrum to obtain a gain-controlled power spectrum (D?(T)). The invention further applies a flooring process to said resultant gain-controlled power spectrum on the basis of arbitrary Flooring factor (?) to obtain a power spectrum for speech recognition (Z?(T)).

Abstract: A semiconductor integrated circuit is provided which is capable of testing a high-speed memory at the actual operation speed of the memory, even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data.

Abstract: A semiconductor integrated circuit has a memory operating on a first clock. A memory device captures first output data, being output from the memory in synchronization with the first clock, depending on a second clock having a frequency equal to or less than the first clock. An expected value comparison section, operating on the second clock, compares second output data being output from the memory device and third output data being output from the memory immediately after the output of the first output data with a predetermined expected value.

Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract: Method and computing apparatus for processing speech signal data. A speech signal is divided into frames. Each frame is characterized by a frame number T representing a unique interval of time. Each speech signal is characterized by a power spectrum with respect to frame T and frequency band ?. A speech segment and a reverberation segment of the speech signal is determined. L filter coefficients W(k) (k=1, 2, . . . , L) respectively corresponding to L frames immediately preceding frame T are computed such that the L filter coefficients minimize a function ? that is a linear combination of sum of squares of a residual speech power in the reverberation segment and a sum of squares of a subtracted speech power in the speech segment. The computed L filter coefficients are stored within storage media of the computing apparatus.

Abstract: For design of a speech interface accepting speech control options, speech samples are stored on a computer-readable medium. A similarity calculating unit calculates a certain indication of similarity of first and second sets of ones of the speech samples, the first set of speech samples being associated with a first speech control option and the second set of speech samples being associated with a second speech control option. A display unit displays the similarity indication. In another aspect, word vectors are generated for the respective speech sample sets, indicating frequencies of occurrence of respective words in the respective speech sample sets. The similarity calculating unit calculates the similarity indication responsive to the word vectors of the respective speech sample sets. In another aspect, a perplexity indication is calculated for respective speech sample sets responsive to language models for the respective speech sample sets.

Abstract: A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.

Abstract: Each of a plurality of redundant memories includes a plurality of memory cells and is operable to be relieved when a defective cell exists. This plurality of redundant memories can operate independently of each other. A relief processing portion is shared by this plurality of redundant memories. A test circuit inspects the plurality of redundant memories. When the test circuit determines that a defective cell exists, the test circuit outputs relief information to relieve the defective cell. The relief processing portion has a plurality of defect relief portions each having a relief information storage portion operable to store the relief information and performs the processing of relieving the plurality of redundant memories.

Abstract: The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data.

Abstract: A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

Abstract: The test method for a semiconductor integrated circuit includes a multi-cycle test step and a single-cycle test step. In the multi-cycle test step, a data-read side flipflop holds data according to a clock enable signal to test a multi-cycle path. In the single-cycle test step, no data is captured for the multi-cycle path.

Abstract: A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

Abstract: An apparatus for testing a semiconductor device by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, including a silicon wiring substrate on which the chip IPs are mounted. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip-flops to wiring, which are arranged to test connections in the wiring. An IP on Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract: A high-quality test pattern for testing a delay fault is generated at a high speed. In order that a second test pattern provided at a test cycle that follows a test cycle should be generated, a fault value set up in a circuit is propagated to an observation point. At a branch point in the circuit, a signal line for propagating the fault value is selected from the branches. Then, activation and justification are performed so that a value of the signal line in the circuit is acquired. When the activation and the justification have been successful, the second test pattern is updated on the basis of the acquired value of the signal line. In the selection of the signal line, one of branches is selected on the basis of the length of the longest path from each branch to the observation point.

Abstract: A semiconductor integrated circuit includes a memory which has redundant lines for repair in both a column direction and a row direction. A test pattern generating section generates a specific test pattern for the memory. A comparing section reads an output from the memory to judge whether or not a fault cell exists in the memory and outputs a signal which shows existence or nonexistence of a faulty cell. The circuit includes a first data storage section, which operates in a first test mode for a test of the memory and a second test mode for a scan test, and a second data storage section which receives an output signal of the comparing section to store a state of presence or absence of a failure corresponding to the existence or nonexistence of the faulty cell. A repair judging section receives an input to the first data storage section and an output of retained contents in the first data storage section and judges that the memory is repairable.

Abstract: A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.

Abstract: A solenoid-operated cutoff valve for use with fuel cells has a movable member disposed in a guide housing for displacement upon energization of a solenoid. When the movable member is displaced, a pilot valve is unseated from a pilot valve seat. A fluid in a communication chamber flows through a pilot passage into an output port. The communication chamber is divided into a first communication chamber and a second communication chamber by a diaphragm. Under a pressure difference developed between the first communication chamber and the second communication chamber, a main valve of a valve head is unseated from a valve seat of a valve housing, opening the solenoid-operated cutoff valve.

Abstract: A user is enabled to obtain a hard copy of a Web page readily when the user browses a Web page using an Internet connection device such as a portable telephone that has no printer connected thereto. A fax transmission request icon is displayed on the Web page. When the user clicks the fax transmission request icon, a fax server is notified of the URL of the Web page and the display screen switches to present the Web page of the fax server. The user then enters his/her member ID for accounting and the fax number of a destination fax machine. The fax server then accesses the notified URL, generates fax output data based on the Web page and sends it to the destination fax machine.

Abstract: A noise reduction device is configured by use of: means for calculating a predetermined constant, and a predetermined reference signal R?(T) in the frequency domain, respectively by use of adaptive coefficients W?(m), and for thereby obtaining estimated values N? and Q?(T) respectively of stationary noise components, and non-stationary noise components corresponding to the reference signal, which are included in a predetermined observed signal X?(T) in the frequency domain; means and for applying a noise reduction process to the observed signal on the basis of each of the estimated values, and for updating each of the adaptive coefficients on the basis of a result of the process; and an adaptive learning means and for repeating the obtaining of the estimated values and the updating of the adaptive coefficients, and for thereby learning each of the adaptive coefficients.