Abstract: A fuel cell system includes a fuel cell, a fluid passage for warming, a gas-liquid separator, a supply passage and a recirculating module. The fuel cell generates power with supply of a reaction gas. The gas-liquid separator separates moisture contained in an anode exhaust gas which is discharged from the fuel cell. The supply passage returns the anode exhaust gas, from which the moisture has been separated by the gas-liquid separator, to an inlet side of the reaction gas. The recirculating module mixes the anode exhaust gas, which is returned via the supply passage, with the reaction gas. The gas-liquid separator lies adjacent to the recirculating module, and the fluid passage for warming is disposed between the gas-liquid separator and the recirculating module.

Abstract: A gas-liquid separator for a fuel cell system onboard a vehicle includes an upper chamber, a lower chamber, a plate for separating the upper and lower chambers, a pipe for circulating the exhaust gas and connecting holes bored in the plate. The upper chamber receives exhaust gas from the fuel cell system to separate water contained in the exhaust gas. The lower chamber has a portion for discharging the water which is separated by the upper chamber. The pipe, which is attached to the upper chamber, has fluid communication with an inside of the upper chamber. The connecting holes provide fluid communication between the upper and lower chambers. The connecting holes are positioned off a center of the plate so that the connecting holes lie apart from the pipe.

Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract: Even when a power switch is turned off, the controller of an injection molding machine does not shut off a power supply immediately. The controller determines whether the present state of the injection molding machine is a previously-set confirmation-requiring state, such as a lockup state of a mold clamping unit using a toggle link mechanism, or a nozzle touch state of an injection unit. When the present state is not the confirmation-requiring state, the controller shuts off the power supply. When the present state is the confirmation-requiring state, the controller displays on a display screen a confirmation window for confirmation of power shut off. The controller shuts off the power supply in accordance with a shut-off operation performed on the basis of the confirmation window.

Abstract: The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data.

Abstract: A door mirror set plate is formed of synthetic resin. On a base plate, a support shaft is vertically provided to rotatively support a door mirror body. A curved surface section is embedded at an outside periphery of a base of the support shaft. A flat section is formed to support a thrust washer so as to cross the curved surface section. Inside the support shaft, there is formed a wiring hole provided with a large diameter section, a small diameter section, and a step section. When a conducting wire is inserted into the wiring hole, the tip of a covering touches the step section for positioning. A stopper and a positioning protrusion are integrally formed on a base plate top surface. The stopper restricts rotational angles of the door mirror body. The positioning protrusion holds the door mirror body at a neutral position.

Abstract: To provide a method of specifying each of speakers of individual voices, based on recorded voices made by a plurality of speakers, with a simple system configuration, and to provide a system using the method. The system includes: microphones individually provided for each of the speakers; a voice processing unit which gives a unique characteristic to each pair of two-channel voice signals recorded with each of the microphones 10, by executing different kinds of voice processing on the respective pairs of voice signals, and which mixes the voice signals for each channel; and an analysis unit which performs an analysis according to the unique characteristics, given to the voice signals concerning the respective microphones through the processing by the voice processing unit, and which specifies the speaker for each speech segment of the voice signals.

Abstract: The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the BIST circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is half the frequency of the first clock.

Abstract: An inventive method is a method for testing a semiconductor integrated circuit that includes a memory circuit provided between a first storage element and a second storage element. The inventive method includes the steps of: (a) initializing the memory circuit; (b) supplying a test pattern to the first storage element; (c) supplying a memory access signal, which corresponds to the test pattern supplied to the first storage element, to the memory circuit through a path that is used in normal operation; (d) capturing a value output from the memory circuit in response to the memory access signal, into the second storage element through a path that is used in normal operation; and (e) comparing the value captured into the second storage element with an expected value.

Abstract: Provision to reduce production of musical noise. A noise reduction device includes: means for calculating a rank for each element included in a first region having predetermined sizes in the time axis direction and in the frequency axis direction, depending on a value of the element, in a noise section of an observed signal indicating variation of a frequency spectrum with time; means for calculating a rank for each element included in a second region, depending on a value of the element, the second region having predetermined sizes in the time axis direction and in the frequency axis direction in the observed signal; and means for subtracting, from the values of the respective elements in the second region, values based on the values of the respective elements in the first region whose ranks correspond to ranks of respective elements in the second region.

Abstract: The test method for a semiconductor integrated circuit includes a multi-cycle test step and a single-cycle test step. In the multi-cycle test step, a data-read side flipflop holds data according to a clock enable signal to test a multi-cycle path. In the single-cycle test step, no data is captured for the multi-cycle path.

Abstract: The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the BIST circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is half the frequency of the first clock.

Abstract: A thin-film semiconductor epitaxial substrate comprising a substrate and a sub-collector layer, a collector layer, a base layer and an emitter layer(s) which are formed as thin-film semiconductor epitaxial layers on said substrate, wherein boron (B) added is present in at least a part of a layer portion comprising said sub-collector layer and said collector layer.

Abstract: A door mirror set plate 1 is formed of synthetic resin. On a base plate 11, a support shaft 12 is vertically provided to rotatively support a door mirror body. A curved surface section 15 is embedded at an outside periphery of a base of the support shaft 12. A flat section 16 is formed to support a thrust washer so as to cross the curved surface section 15. Inside the support shaft 12, there is formed a wiring hole 18 provided with a large diameter section 19, a small diameter section 21, and a step section 22. When a conducting wire is inserted into the wiring hole 18, the tip of a covering touches the step section 22 for positioning. A stopper 25 and a positioning protrusion 26a are integrally formed on a base plate top surface 11a. The stopper 25 restricts rotational angles of the door mirror body. The positioning protrusion 26a holds the door mirror body at a neutral position.

Abstract: Enables the estimation of a sound source position at an angle in a system with a small number of microphones, which was conventionally difficult to perform, and improve the precision of estimating the sound source position. By forming a reflecting surface RS as an enveloping surface of a spheroid in which a position of sound collecting means and a sound source position are the focal points, a major reflected wave having a delay amount corresponding to a sound source position is generated, and the delay amount between the direct wave and the reflected wave is checked, whereby the sound source position is acquired and estimated.

Abstract: In order to achieve a redundant repair for a memory using a BIST, a semiconductor integrated circuit which can suppress an increase in circuit area for redundant repair and circuit area for scan test, and an test method thereof are provided.

Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract: Even when a power switch is turned off, the controller of an injection molding machine does not shut off a power supply immediately. The controller determines whether the present state of the injection molding machine is a previously-set confirmation-requiring state, such as a lockup state of a mold clamping unit using a toggle link mechanism, or a nozzle touch state of an injection unit. When the present state is not the confirmation-requiring state, the controller shuts off the power supply. When the present state is the confirmation-requiring state, the controller displays on a display screen a confirmation window for confirmation of power shut off. The controller shuts off the power supply in accordance with a shut-off operation performed on the basis of the confirmation window.