Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract: The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the BIST circuit of the integrated circuit is restricted.

Abstract: A thin-film semiconductor epitaxial substrate comprising a substrate and a sub-collector layer, a collector layer, a base layer and an emitter layer(s) which are formed as thin-film semiconductor epitaxial layers on said substrate, wherein boron (B) added is present in at least a part of a layer portion comprising said sub-collector layer and said collector layer.

Abstract: Provided is a method for canceling background noise of a sound source other than a target direction sound source in order to realize highly accurate voice recognition, and a system using the same. In terms of directional characteristics of a microphone array, due to a capability of approximating a power distribution of each angle of each of possible various sound source directions by use of a sum of coefficient multiples of a base form angle power distribution of a target sound source measured beforehand by base form angle by using a base form sound, and power distribution of a non-directional background sound by base form, only a component of the target sound source direction is extracted at a noise suppression part. In addition, when the target sound source direction is unknown, at a sound source localization part, a distribution for minimizing the approximate residual is selected from base form angle power distributions of various sound source directions to assume a target sound source direction.

Abstract: In response to a design request, fault detection strategy optimizing means selects RT-VCs and a fault detection method from a VCDB. The design request includes: requirements for a system LSI (e.g., area, number of pins, test time and information about the weights of prioritized constraints); and VC information. The fault detection strategy optimizing means performs computations for optimization in view of various parameters, thereby specifying a best fault detection strategy and a method of constructing a single-chip fault detection controller. On the VCDB, multiple VCs associated with the same function and mutually different test techniques are stored. By weighting the parameters affecting a test cost in accordance with a user defined priority order, a test technique of the type minimizing the total test cost can be selected from the VCDB.

Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract: Removing particles and metallic contaminants without corrosing the metallized wirings and without giving adverse effect of planarization on the semiconductor substrate surface can be effectively achieved by use of a cleaning agent which comprises an organic acid having at least one carboxyl group and a complexing agent having chelating ability.

Abstract: A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

Abstract: Removing particles and metallic contaminants without corrosing the metallized wirings and without giving adverse effect of planarization on the semiconductor substrate surface can be effectively achieved by use of a cleaning agent which comprises an organic acid having at least one carboxyl group and a complexing agent having chelating ability.

Abstract: A user is enabled to obtain a hard copy of a Web page readily when the user browses a Web page using an Internet connection device such as a portable telephone that has no printer connected thereto. A fax transmission request icon is displayed on the Web page. When the user clicks the fax transmission request icon, a fax server is notified of the URL of the Web page and the display screen switches to present the Web page of the fax server. The user then enters his/her member ID for accounting and the fax number of a destination fax machine. The fax server then accesses the notified URL, generates fax output data based on the Web page and sends it to the destination fax machine.

Abstract: Removing particles and metallic contaminants without corrosing the metallized wirings and without giving adverse effect of planarization on the semiconductor substrate surface can be effectively achieved by use of a cleaning agent which comprises an organic acid having at least one carboxyl group and a complexing agent having chelating ability.

Abstract: A semiconductor IC includes a test circuit comprising a logic circuit, a test timing generator, a first register serving as a test signal generation point, and second and third registers serving as test signal observation points. In this test circuit, a target signal transmission path to be tested is selected from a plurality of signal transmission paths in the logic circuit, and the test timing generator outputs a test clock having a cycle according to a delay time of the selected signal transmission path on design to the first to third registers, whereby the first register generates a test signal and the second and third registers observe the test signal. Therefore, the signal transmission paths connecting the test signal generation point and the test signal observation point are tested with high efficiency, whereby more signal transmission paths are tested for delay faults with less number of times the test is executed.

Abstract: Removing particles and metallic contaminants without corrosing the metallized wirings and without giving adverse effect of planarization on the semiconductor substrate surface can be effectively achieved by use of a cleaning agent which comprises an organic acid having at least one carboxyl group and a complexing agent having chelating ability.

Abstract: Disclosed is a computer system having a ring buffer arrangement which includes a plurality of sub-rings and a main ring. Each of the sub-rings includes a plurality of buffer memories and the main ring includes a plurality of the sub-rings. A main write pointer and a main read pointer are provided for the main ring in order to indicate a sub-ring for which data writing and data reading are currently being performed respectively. A sub-write pointer and a sub-read pointer are provided for each sub-ring in order to indicate, for the sub-ring, a buffer memory for which data writing and data reading are currently being executed respectively. Since the total size of the double ring buffer is large, not all of the buffer memories can be resident in physical memory. However, since the number of buffer memories included in a single sub-ring is relatively small, one sub-ring can be resident in the physical memory.

Abstract: A control system is applicable for an injection molding machine which has a temperature setting function and display function. The control system includes a temperature scale/unit setting function for selecting a temperature setting and a displaying mode which changes a data display between a Centigrade mode (where a temperature setting device and temperature on the display are performed in Centigrade) and a Fahrenheit mode. The control system also includes a display switching function for temporarily switching the display mode to a mode different from the current temperature setting mode as set by the temperature scale/unit setting function and a display mode restoring function for switching the temporarily switched display mode to the original display mode.

Abstract: In a thin-type liquid crystal display device of this invention, a display section is formed on a printed circuit board and has a matrix array of display cells, address lines connected to the row arrays of the display cells and data lines connected to the column arrays of the disply cells. Row and column switching selectors are provided on the printed circuit board. The respective selectors include a parallel array of switches, such as TFTs. The row selector is connected to the address lines for sequentially selecting address lines through a scanning operation for image display. The column selector is connected to the data line for subjecting an incoming frame of image data to a time-division multiplexing and for sequentially supplying block-segmented image data components to the data lines.

Abstract: In a waterproof optical fiber cable for use in a communication system, one or more optical fibers are loosely put in grooves formed along a spacer and a plurality of filled portions are formed in each of said grooves by being filled with dampproof material with a predetermined interval so as to provide a plurality of filled portions and unfilled portions alternately, whereby undesired local bending of the optical fibers can be prevented. Also a method of making the waterproof optical fiber cable having such filled portions and unfilled portions is disclosed.

Abstract: An optical fiber cable for detecting a low temperature comprising a center member made of a material having a low coefficient of linear expansion and one or more longitudinally extending grooves in each of which at least one optical fiber is placed, (i) wherein at least one optical fiber comprising a core and a cladding both made of silica glass is placed in each of said grooves and the interior space of the groove which is not occupied by the optical fiber or fibers may be filled with a resin which has a low glass transition temperature; or (ii) wherein each of the optical fibers placed in each of said grooves, have different coating structures from each other and/or different fiber structures from each other so as to detect a low temperature in different temperature ranges.

Abstract: In a waterproof optical fiber cable for use in a communication system, one or more optical fibers are loosely put in grooves formed along a spacer and a plurality of filled portions are formed in each of said grooves by being filled with dampproof material with a predetermined interval so as to provide a plurality of filled portions and unfilled portions alternately, whereby undesired local bending of the optical fibers can be prevented. Also a method of making the waterproof optical fiber cable having such filled portions and unfilled portions is disclosed.

Abstract: A display device having a display array of m.times.n display elements driven by a static shift register having m.times.n stages respectively corresponding to row and column designations of the display elements. The column lines of the display element array are driven by a first output of the m stages. At the same time, pixel data are supplied to the shift register in accordance with a binary level of an externally supplied select signal. Alternatively, the shift register is shifted in a recursive manner. The row lines of the display element array are scanned in accordance with a count of a clock signal. Select signal lines and clock signal lines are respectively aligned along the row and column directions of a unit panel when plural display arrays as described above are arranged in a matrix form to provide a large-screen display unit. The lines of each display array are sequentially driven in accordance with the supply pattern of the select and clock signals from a corresponding unit driver.