Patents by Inventor Pan Wang

Pan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180342502
    Abstract: A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.
    Type: Application
    Filed: January 30, 2018
    Publication date: November 29, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Kuan Su, Yu-Hong Pan, Jen-Pan Wang, Tong-Min Weng, Tsung-Han Wu
  • Patent number: 10062603
    Abstract: The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant. In some embodiments, the BEOL metallization stack has an inter-level dielectric (ILD) layer disposed over a substrate. A metal interconnect layer is disposed within the ILD layer, and an air gap is arranged disposed within the ILD layer at a position between a first feature and a second feature of the metal interconnect layer. The air gap has an upper surface with a first curve that meets a second curve at a peak arranged below a top of the metal interconnect layer. The first curve becomes steeper as a distance from the peak decreases and the second curve becomes steeper as a distance from the peak decreases.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Chih-Fu Chang, Jen-Pan Wang
  • Patent number: 10053985
    Abstract: The invention discloses a real-time water-level monitoring system for a dumping site of an open-pit coal mine. The dumping site of the open-pit coal mine comprises an aboveground part and an underground part, where the aboveground part is a stacking site (1) located above an original ground surface. The real-time water-level monitoring system for a dumping site of an open-pit coal mine comprises a first measuring well (2) and a second measuring well (3), where the first measuring well (2) is arranged vertically in the center of the stacking site (1), and the second measuring well (3) includes a vertical section (301), a horizontal section (302), and a free section (303) connected in sequence; and a first water-impermeable layer (4), a second water-impermeable layer (5), and a third water-impermeable layer (6) are provided internally in the stacking site (1).
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 21, 2018
    Assignee: CHINA UNIVERSITY OF MINING & TECHNOLOGY-BEIJING
    Inventors: Suping Peng, Feisheng Feng, Pingjie Fu, Wenfeng Du, Pan Wang
  • Patent number: 10018789
    Abstract: A method and an apparatus for coupling an optical waveguide to a single-mode fiber are disclosed. The apparatus includes a substrate, a first optical waveguide, a single-mode fiber and a second optical waveguide. The first optical waveguide, the single-mode fiber and the second optical waveguide dispose on the substrate. One end of the single-mode fiber has an optical fiber taper structure. One end of the second optical waveguide is optically coupled to the first optical waveguide. Another end of the second optical waveguide is optically coupled to the single-mode fiber using the optical fiber taper structure of the single-mode fiber.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: July 10, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Pan Wang, Can Zhang, Qinfen Hao
  • Patent number: 10008501
    Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Patent number: 9978744
    Abstract: A passive device and method of fabricating the passive device are disclosed herein. The capacitor structure incorporates a resistor and a capacitor. An exemplary method includes receiving a substrate that has undergone front end of line (FEOL) processing, and performing back end of line (BEOL) processing on the substrate, wherein a capacitor structure is formed over the substrate during the BEOL processing, the capacitor structure incorporating a resistor with a capacitor. The BEOL processing can include performing a first metallization process to form a bottom plate of the capacitor structure; forming a dielectric spacer of the capacitor structure over the bottom plate; forming a top plate of the capacitor structure over the dielectric spacer; and performing a second metallization process to form contacts coupled to the top plate and the bottom plate of the capacitor structure.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Fu Chang, Jen-Pan Wang
  • Publication number: 20180127859
    Abstract: In an example of a method for increasing strength of an aluminum alloy, the aluminum alloy is formed in a molten state. The aluminum alloy includes from about 4 wt % to about 11 wt % silicon, from greater than 0.2 wt % to about 0.5 wt % chromium, from about 0.1 wt % to about 0.5 wt % magnesium, from about 0.01 wt % to about 0.1 wt % titanium, equal to or less than about 0.5 wt % iron, equal to or less than about 0.5 wt % manganese, and a balance of aluminum. The aluminum alloy is subjected to a solution heat treatment. The aluminum alloy is quenched, and the aluminum alloy is age hardened at an age hardening temperature ranging from about 140° C. to 175° C. for a time period ranging from about 3 hours to about 35 hours.
    Type: Application
    Filed: November 8, 2016
    Publication date: May 10, 2018
    Inventors: Bin Hu, Pan Wang, Qi Lu
  • Patent number: 9896746
    Abstract: A method for preparing element diffusion-type composite substrate and it belongs to the field of high-temperature coated superconductor substrate preparation. The rolled composite nickel-tungsten alloy substrate is heated and thermally insulated, meanwhile, both ends of the rolled substrate are applied with a low voltage and high current density pulse current. High-performance nickel-tungsten alloy composite substrate is obtained with the method in the present invention and the sandwich-like composite substrate has low ferromagnetism and high strength due to higher solute diffusion from inner layer to outer layer, yet which does not affect the formation of sharp cubic texture on the surface of the composite substrate.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: February 20, 2018
    Assignee: BEIJING UNIVERSITY OF TECHNOLOGY
    Inventors: Hongli Suo, Yichen Meng, Lin Ma, Min Liu, Yi Wang, Mangmang Gao, Hui Tian, Yaru Liang, Pan Wang, Faxue Peng, Jing Liu, Tiantian Wang
  • Publication number: 20180026091
    Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 25, 2018
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
  • Publication number: 20180002348
    Abstract: The present invention provides a novel phenothiazine-pyridine compound that is an effective photosensitizer useful for photodynamic therapy. Also provided is a method for inhibiting cell proliferation or for treating a disease involving inappropriate cell proliferation.
    Type: Application
    Filed: May 8, 2017
    Publication date: January 4, 2018
    Inventors: Chuanshan Xu, Qicai Xiao, Wing Nang Leung, Pan Wang, Hungkay Lee
  • Patent number: 9768243
    Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
  • Publication number: 20170191432
    Abstract: A method of controlling speed of an internal combustion engine is disclosed. The method includes receiving a load parameter input. The method also includes determining a requested speed demand and detecting a change in load based on the load parameter input. The method also includes determining a modified speed demand based on the detected change in load, and modifying the requested speed demand to the modified speed demand.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 6, 2017
    Applicant: Cummins, Inc.
    Inventors: Roger S. Zhang, Pan Wang, Joey Wang
  • Patent number: 9599888
    Abstract: Various non-planar reflective lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a transparent substrate, a reflective material, and a reticle pattern. The transparent substrate comprises a curved surface. The reflective material adjoins the curved surface of the transparent substrate, and an interface between the reflective material and the transparent substrate is a reflective surface. The reticle pattern is on a second surface of the transparent substrate. A reflectivity of the reticle pattern is less than a reflectivity of the reflective material. Methods for forming similar lithography masks and for using similar lithography masks are disclosed.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsuan Liu, Jen-Pan Wang
  • Publication number: 20170005095
    Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.
    Type: Application
    Filed: September 16, 2016
    Publication date: January 5, 2017
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Publication number: 20160336216
    Abstract: The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant. In some embodiments, the BEOL metallization stack has an inter-level dielectric (ILD) layer disposed over a substrate. A metal interconnect layer is disposed within the ILD layer, and an air gap is arranged disposed within the ILD layer at a position between a first feature and a second feature of the metal interconnect layer. The air gap has an upper surface with a first curve that meets a second curve at a peak arranged below a top of the metal interconnect layer. The first curve becomes steeper as a distance from the peak decreases and the second curve becomes steeper as a distance from the peak decreases.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 17, 2016
    Inventors: Ru-Shang Hsiao, Chih-Fu Chang, Jen-Pan Wang
  • Patent number: 9478466
    Abstract: A method comprises removing a dummy gate electrode layer to form a gate trench in a dielectric layer over a substrate, forming a resistor trench over the substrate, depositing a plurality of films on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a gate electrode layer over the plurality of films and removing an upper portion of the gate electrode layer until the gate electrode layer is removed from the resistor trench.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang
  • Publication number: 20160299294
    Abstract: A method and an apparatus for coupling an optical waveguide to a single-mode fiber are disclosed. The apparatus includes a substrate, a first optical waveguide, a single-mode fiber and a second optical waveguide. The first optical waveguide, the single-mode fiber and the second optical waveguide dispose on the substrate. One end of the single-mode fiber has an optical fiber taper structure. One end of the second optical waveguide is optically coupled to the first optical waveguide. Another end of the second optical waveguide is optically coupled to the single-mode fiber using the optical fiber taper structure of the single-mode fiber.
    Type: Application
    Filed: June 20, 2016
    Publication date: October 13, 2016
    Inventors: Pan Wang, Can Zhang, Qinfen Hao
  • Patent number: 9466670
    Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Patent number: 9449811
    Abstract: The present disclosure relates a method of forming a back-end-of-the-line (BEOL) metallization layer having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant, and an associated apparatus. In some embodiments, the method is performed by forming a metal interconnect layer within a sacrificial dielectric layer overlying a substrate. The sacrificial dielectric layer is removed to form a recess extending between first and second features of the metal interconnect layer. A protective liner is formed onto the sidewalls and bottom surface of the recess, and then a re-distributed ILD layer is deposited within the recess in a manner that forms an air gap at a position between the first and second features of the metal interconnect layer. The air gap reduces the dielectric constant between the first and second features of the metal interconnect layer.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ru-Shang Hsiao, Chih-Fu Chang, Jen-Pan Wang
  • Publication number: 20160268253
    Abstract: A passive device and method of fabricating the passive device are disclosed herein. The capacitor structure incorporates a resistor and a capacitor. An exemplary method includes receiving a substrate that has undergone front end of line (FEOL) processing, and performing back end of line (BEOL) processing on the substrate, wherein a capacitor structure is formed over the substrate during the BEOL processing, the capacitor structure incorporating a resistor with a capacitor. The BEOL processing can include performing a first metallization process to form a bottom plate of the capacitor structure; forming a dielectric spacer of the capacitor structure over the bottom plate; forming a top plate of the capacitor structure over the dielectric spacer; and performing a second metallization process to form contacts coupled to the top plate and the bottom plate of the capacitor structure.
    Type: Application
    Filed: May 25, 2016
    Publication date: September 15, 2016
    Inventors: Chih-Fu Chang, Jen-Pan Wang