Abstract: A system including a first cell, a second cell, a first switch, a second switch, an inductance, and a control module. The first cell and the second cell are connected in series to each other and respectively output a first voltage and a second voltage. The first switch and the second switch are connected in series to each other and are connected across the first cell and the second cell. The inductance is connected between the first switch and the second switch, and between the first cell and the second cell. The control module generates control signals to control the first switch and the second switch, and to transfer charge between the first cell and the second cell via the inductance until a difference between the first voltage and the second voltage is less than or equal to a predetermined threshold. The predetermined threshold is not equal to zero.

Abstract: A system including a write module, a read module, and a signal processing module. The write module is configured to write pilot data, having a first predetermined pattern, in a page of memory cells. The pilot data are interspersed with user data stored in the page. The read module is configured to read the pilot data and to generate pilot signals based on reading the pilot data. The signal processing module is configured to compare the pilot signals and the pilot data, and to estimate, based on a comparison of the pilot signals and the pilot data, a disturbance to the user data.

Abstract: A calibration module generates a plurality of calibration codes respectively for a first plurality of transistors located along (i) a plurality of bit lines and (ii) a first word line of a memory array. Each of the calibration codes is based on a distance of a corresponding one of the plurality of bit lines from an input of the first word line. A voltage generator outputs a first voltage generated based on a first plurality of codewords to an input of a second word line. A control module determines values of threshold voltages of a second plurality of transistors located along (i) the plurality of bit lines and (ii) the second word line based on (a) the first plurality of codewords and (b) currents sensed through the second plurality of transistors, and adjusts the values of the threshold voltages based on the calibration codes.

Abstract: A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell.

Abstract: A system including a resistive random access memory cell connected to a word line and a bit line and a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected. A driver circuit selects the word line at a first time subsequent to the bit line being charged to the first voltage. A comparator compares a second voltage on the bit line to a third voltage supplied to the comparator and generates an output based on the comparison. A latch latches the output of the comparator and generates a latched output. A pulse generator generates a pulse after a delay subsequent to the first time to clock the latch to latch the output of the comparator and generate the latched output. The latched output indicates a state of the resistive random access memory cell.

Abstract: A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch.

Abstract: A system includes a resistive random access memory cell and a driver circuit. The resistive random access memory cell includes a resistive element and a switching element, and has a first terminal connected to a bit line and a second terminal connected to a word line. The driver circuit is configured to apply, in response to selection of the resistive random access memory cell using the word line, a first voltage of a first polarity to the bit line to program the resistive random access memory cell to a first state by causing current to flow through the resistive element in a first direction, and a second voltage of a second polarity to the bit line to program the resistive random access memory cell to a second state by causing current to flow through the resistive element in a second direction.

Abstract: A cell of a resistive random access memory including a resistive element and an access device. The resistive element includes (i) a first electrode and (ii) a second electrode. The access device is configured to select and deselect the cell. The access device includes (i) a first terminal connected to a first contact and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact includes (i) a first surface in contact with the second contact and (ii) a second surface in contact with the second electrode. The first surface defines a first surface area, and the second surface defines a second surface area. The first surface area is greater than the second surface area.

Abstract: In at least one aspect, an apparatus includes a plurality of inverter groups and a plurality of bias current sources. The plurality of inverter groups is configured to amplify a signal. Each of the inverter groups has one or more inverters and is in communication with at least one other inverter group of the plurality of inverter groups. Each of the bias current sources is configured to provide a bias current to a different inverter group of the plurality of inverter groups to perform signal amplification.

Abstract: A system includes a position detection module configured to detect at least a first position indicator and a second position indicator corresponding to a label side of an optical disc. A write clock adjustment module is configured to determine a number of cycles of a write clock that occur between the first position indicator and the second position indicator, determine a difference between the number of cycles of the write clock and a desired number of cycles of the write clock, and adjust a frequency of the write clock based on the difference.

Abstract: A memory array includes a plurality of sense amplifiers and a first switch module. The plurality of sense amplifiers is connected respectively to a plurality of global bit lines. The plurality of sense amplifiers are configured to read data stored in a first block of memory cells of the memory array. The memory cells in the first block are located at intersections of a plurality of local bit lines and a first plurality of word lines. The first switch module is connected to a first group of the plurality of local bit lines and to a first group of the plurality of global bit lines. The first switch module is configured to selectively connect a subset of the first group of the plurality of local bit lines to the first group of the plurality of global bit lines.

Abstract: Systems, methods, and other embodiments associated with providing contextual content along with elements within an application are described. According to one embodiment, an apparatus includes icon logic configured to generate, in response to detecting a selection of a page element, an icon that indicates whether contextual content associated with the page element is available. The page element is a display element of a graphical user interface (GUI) for an application. The apparatus includes context logic configured to generate a context panel in response to detecting an input associated with the icon. The context logic is configured to generate the context panel with a first tab and a second tab. The first tab includes a description of the page element and the second tab includes a set of comments from users about the page element.

Abstract: A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.

Abstract: A system including a processor, a FIFO, and an arbiter module. The processor includes a processor core and a memory. The processor core processes data stored in a memory and executes instructions using the memory. The FIFO receives streaming data and outputs the streaming data to the memory. The arbiter module, in response to the FIFO not being filled to a predetermined threshold, allows the processor core to access the memory at a higher priority than the FIFO to permit the processor core to process data including any streaming data stored in the memory, and to execute instructions using the memory. The arbiter module, in response to the FIFO being filled to the predetermined threshold, allows the FIFO to access the memory at the higher priority than the processor core to permit the FIFO to output the streaming data, without having the FIFO overflow, to the memory.

Abstract: A method for reducing a disturbance associated with repeatable runout associated with a removable disc loaded into a storage system. The method includes, at the storage system: logically partitioning the removable disc into sectors; for each of the sectors, obtaining a corresponding profile of repeatable runout contained in the sector; and applying a runout control algorithm to each of the sectors to generate a repeatable runout control (RROC) waveform that is usable to suppress the repeatable runout in the sector as indicated by the profile corresponding to the sector. The method also includes, at the storage system: assembling each RROC waveform to generate a single RROC waveform that is useable to suppress repeatable runout as contained in an entire revolution of the removable disc; and storing, in a memory, the single RROC waveform.

Abstract: A system includes a read channel circuit configured to output a write signal, and output a write enable signal that indicates a write operation. A preamplifier circuit includes a write amplifier configured to amplify the write signal and provide the amplified write signal to a read/write device. A read amplifier is configured to amplify a read signal received from the read/write device. A circuit is configured to receive the amplified write signal from the write amplifier, receive the amplified read signal from the read amplifier, receive the write enable signal from the read channel circuit, and provide, to the read channel circuit, a selected one of the amplified write signal and the amplified read signal based on the write enable signal.

Abstract: A method of operating a memory system, including charge storage cells arranged into blocks, includes receiving a read request from a host that designates a location to be read within a first block. The method includes, in response to the read request, making measurements on the location to be read and responding to the host based on the measurements. The method includes receiving a write request from the host that designates a location to be written within the first block. The method includes, in response to the write request, selectively erasing the first block and resetting a timer. The method includes, in response to either the timer exceeding a predetermined time, or the measurements being outside of a predetermined range, refreshing the first block and resetting the timer. Refreshing the first block comprises adjusting charge levels in the charge storage cells of the first block without erasing the first block.

Abstract: A memory chip includes a plurality of storage elements. A method of controlling the memory chip includes receiving a plurality of target values from a memory controller. Each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements. The method further includes, for each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller.

Abstract: A system including a plurality of cells connected in series in a rechargeable battery pack and a plurality of cell balancing modules. Each cell balancing module performs voltage balancing of a respective pair of cells. Each cell balancing module includes a communication module to (i) transmit, via a communication link, information about voltages of the respective pair of cells to an adjacent cell balancing module and (ii) receive, via the communication link, from the adjacent cell balancing module, information about voltages of cells corresponding to the adjacent cell balancing module. Each cell balancing module performs, based on the information received from the adjacent cell balancing module, the voltage balancing in response to a voltage difference between any of the plurality of cells being greater than or equal to a predetermined threshold instead of performing the voltage balancing based on a difference between voltages of the respective pair of cells.

Abstract: Methods, systems, and apparatus include, in one aspect, a method including receiving from a controller a signal for controlling a device for rotating a machine-readable medium; and increasing a bandwidth of a transfer function corresponding to the controller by at least filtering the signal to compensate for a pole of the transfer function.