Abstract: To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.

Abstract: Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of a pattern, the first subset configured to form a plurality of lines over the substrate, and patterning a second subset of the pattern, the second subset configured to form a plurality of islands over the substrate, wherein said patterning the first subset and said patterning the second subset comprise at least two separate patterning operations.

Abstract: A calibration module generates a plurality of calibration codes respectively for a first plurality of transistors located along (i) a plurality of bit lines and (ii) a first word line of a memory array. Each of the calibration codes is based on a distance of a corresponding one of the plurality of bit lines from an input of the first word line. A voltage generator outputs a first voltage generated based on a first plurality of codewords to an input of a second word line. A control module determines values of threshold voltages of a second plurality of transistors located along (i) the plurality of bit lines and (ii) the second word line based on (a) the first plurality of codewords and (b) currents sensed through the second plurality of transistors, and adjusts the values of the threshold voltages based on the calibration codes.

Abstract: A system including a converter, a first filter, a first device, a second filter, and a second device. The converter samples an input signal at multiple sampling times to generate samples. The first filter includes a first taps, which receive first tap weight coefficients. The first filter filters the samples to generate a first output signal based on the first tap weight coefficients. The first device, based on the samples of the input signal, updates the first tap weight coefficients. The second filter includes second taps, which receive second tap weight coefficients. The second filter filters the first output signal to generate a second output signal based on the second tap weight coefficients. The second device, based on the first output signal, updates the second tap weight coefficients. The input signal is sampled based on the second output signal of the second filter.

Abstract: Some of the embodiments of the present disclosure provide a disk drive system comprising a disk drive system comprising a disk having a track upon a surface of the disk, the track including a first data-storing sector and a second data storing sector, and a servo sector located between the first data-storing sector and the second data-storing sector, the servo sector including a first flying height (FH) field having a predetermined pattern. Other embodiments are also described and claimed.

Abstract: Aspects of the disclosure provide a method. The method includes detecting a dimming characteristic in an energy source that provides energy to be transferred to a load via a magnetic component, receiving a dimming control signal, and controlling a switch in connection with the magnetic component based on the dimming characteristic and the dimming control signal to transfer energy to the load via the magnetic component.

Abstract: A system including a first cell, a second cell, a first switch, a second switch, an inductance, and a control module. The first cell and the second cell are connected in series to each other and respectively output a first voltage and a second voltage. The first switch and the second switch are connected in series to each other and are connected across the first cell and the second cell. The inductance is connected between the first switch and the second switch, and between the first cell and the second cell. The control module generates control signals to control the first switch and the second switch, and to transfer charge between the first cell and the second cell via the inductance until a difference between the first voltage and the second voltage is less than or equal to a predetermined threshold. The predetermined threshold is not equal to zero.

Abstract: A data processing module includes a first interface connected to (i) a host via a second interface, and (ii) storage arrays. The first interface receives, from the host via the second interface, blocks of data for storage in one or more of the storage arrays. A memory stores the blocks of data received by the first interface. A processor (i) determines error checking and correcting processing to be applied to each block of data of the blocks of data, and (ii) for each block of data, (a) transfers the block of data from the memory to a selected storage array of the storage arrays, and (b) assigns, to the selected storage array, the error checking and correcting processing to be applied to the block of data. The memory stores a map. The map indicates storage of the blocks of data among the storage arrays.

Abstract: Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.

Abstract: A system including a control module, error modules, and a tracking module. The control module: transitions a laser beam between positions on an storage medium; based on a tracking signal, adjusts a speed that the laser beam is transitioned, and while the laser beam is transitioned, increases the speed that the laser beam is transitioned from a first speed to a second speed. The error modules determine a track error of a current position of the laser beam and estimate a depth of a groove. The tracking module: while the speed of the laser beam is equal to the first speed, tracks the current position based on the track error and the depth of the groove; while the speed of the laser beam is equal to the second speed, tracks the current position based on the track error; and generates the tracking signal based on the current position.

Abstract: A memory array includes a plurality of sense amplifiers and a first switch module. The plurality of sense amplifiers is connected respectively to a plurality of global bit lines. The plurality of sense amplifiers are configured to read data stored in a first block of memory cells of the memory array. The memory cells in the first block are located at intersections of a plurality of local bit lines and a first plurality of word lines. The first switch module is connected to a first group of the plurality of local bit lines and to a first group of the plurality of global bit lines. The first switch module is configured to selectively connect a subset of the first group of the plurality of local bit lines to the first group of the plurality of global bit lines.

Abstract: A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.

Abstract: A system includes a hard disk controller configured to, using only a single pin, transfer serial information from the hard disk controller. The serial information includes control data associated with control of both write operations and read operations. The serial information includes a first bit indicating a start of the control data, a predetermined number of bits of the control data following the first bit, and a second bit indicating an end of the predetermined number of bits of the control data. A read/write channel is configured to receive the serial information and perform the write operations and the read operations based on the serial information.

Abstract: A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is stored in the NV memory. A product code codeword is based on the codewords in the first dimension and the codewords in the second dimension.

Abstract: A data channel circuit including an analog to digital converter, a timing loop control circuit, an interpolator circuit, and a deglitch circuit. The analog to digital converter is configured to convert an analog input signal into a corresponding digital signal in accordance with a reference clock signal received from a timing loop. The timing loop control circuit is configured to receive the digital signal from the analog to digital converter, and generate a first clock signal based on the digital signal. The interpolator circuit is configured to receive the first clock signal, and generate a second clock signal based on the first clock signal, and the first clock signal delayed by a predetermined phase delay. The second clock signal has first glitches. The deglitch circuit is configured to, based on the second clock signal, generate the reference clock signal. The reference clock signal does not include the first glitches.

Abstract: Methods, software, and apparatuses for reading from and/or writing to an optical storage medium. The methods generally include steps for reading a region of an optical storage medium to produce a readback signal, processing predetermined pattern data to produce one or more measurement instructions, measuring one or more characteristics of the readback signal in response to the measurement instructions to produce one or more measurement results, and further processing the readback signal in accordance with one or more of the measurement results. Thus, the ability to flexibly set test parameters and to quickly and accurately test the write characteristics of a recordable or re-writable optical storage medium is provided.

Abstract: An on-chip capacitor includes a first layer first polarity conducting strip and a first layer second polarity conducting strip, wherein the first layer second polarity conducting strip is arranged adjacent to and spaced apart from the first layer first polarity conducting strip, a second layer first polarity conducting strip and a second layer second polarity conducting strip, wherein the second layer second polarity conducting strip is arranged adjacent to and spaced apart from the second layer first polarity conducting strip, wherein the second layer second polarity conducting strip is arranged overlying the first layer second polarity conducting strip, wherein the second layer first polarity conducting strip is arranged overlying the first layer first polarity conducting strip; wherein the first layer first-polarity conducting strip electrically couples with the second layer first polarity conducting strip; and wherein the first-layer second polarity conducting strip electrically couples with the second la

Abstract: A system includes chips and a control module. Each of the chips includes an array of memory cells. Each of the arrays of memory cells includes rows of memory cells. Each of the rows of memory cells is configured to store a predetermined amount of data. The control module is configured to receive data, encode the data to generate blocks of encoded data, store a first portion of one of the blocks of encoded data in a first selected number row of a first chip, and store a remaining portion of the one of the blocks of encoded data in a second selected number row of a second chip. An amount of data in each of the blocks of encoded data is more than the predetermined amount of data. The second selected number row is a same number row or a higher number row than the first selected number row.

Abstract: A system-on-a-chip including a first one-time-programmable memory, a second memory, a test interface, an input circuit, and a processor. The input circuit is configured to receive data transmitted from a third memory to the system-on-a-chip. The processor is configured to, while booting up the system-on-a-chip, determine whether a first one-time-programmable memory has been previously programmed. The processor is also configured to (i) in response to the first one-time-programmable memory not having been previously programmed, enable the test interface for debugging of the system-on-a-chip, (ii) based on the first one-time-programmable memory having been previously programmed, disable the test interface, and (iii) subsequent to one of the enabling of the test interface and the disabling of the test interface, load the data from the third memory into the second memory.

Abstract: A memory chip includes a plurality of storage elements. A method of controlling the memory chip includes receiving a plurality of target values from a memory controller. Each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements. The method further includes, for each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller.