Abstract: A system includes a sensing module and a switching module. The sensing module is configured to sense output voltages of first and second cells connected in series in a rechargeable battery stack. The switching module is configured to alternately connect a capacitance across the first cell and the second cell at a switching frequency when a difference in the output voltages is greater than or equal to a first threshold. The switching module is further configured to stop alternately connecting the capacitance when the difference is less than or equal to a second threshold, wherein the first threshold is greater than the second threshold.

Abstract: A system including a hard disk control circuit, a read channel circuit, and a preamplifier circuit. The hard disk control circuit is configured to generate a first symbol. The read channel circuit configured to encode the first symbol to generate an encoded symbol. The preamplifier circuit configured to operate in a loopback mode. While operating in the loopback mode, the preamplifier circuit is configured to amplify the encoded symbol and transmit the encoded symbol back to the read channel circuit. The read channel circuit is configured to decode the encoded symbol to generate a second symbol and provide the second symbol to the hard disk control circuit. The hard disk control circuit is configured to perform a comparison between the first symbol and the second symbol and generate an indication of whether the preamplifier circuit is operating properly based on the comparison between the first symbol and the second symbol.

Abstract: Systems and techniques relating to writing servo information on a machine-readable medium include a method that includes writing a first set of sloped tracks to a first surface of at least one rotatable recording medium having at least two associated transducers, writing a second set of sloped tracks to a second surface of the at least one rotatable recording medium, and writing servo information to the at least one rotatable recording medium using the first and second sets of sloped tracks, wherein the first surface is distinct from the second surface. Further, an apparatus includes an input, an output, and signal processing circuitry comprising one or more control units configured to cause writing of first and second sets of sloped tracks and servo information using the first and second sets of sloped tracks.

Abstract: A controller for a laser driver includes a parameter generation module, a timing encoding module, and a pulse generation module. The parameter generation module is configured to, for each mark contained in a bit stream, generate a set of timing parameters based on defining characteristics of the bit stream. The defining characteristics include length of the mark and at least one of (i) a length of a leading space prior to the mark and (ii) a length of a following space subsequent to the mark. The timing encoding module is configured to determine a plurality of pulse defining parameters based on the set of timing parameters. The pulse generation module is configured to create a plurality of pulses based on the plurality of pulse defining parameters, combine the plurality of pulses into a plurality of enable signals, and output the plurality of enable signals to the laser driver.

Abstract: A charge-balancing system includes N circuits and a control module, where N is an integer greater than or equal to 1. Each of the N circuits includes first and second switches connected in series and an inductance having a first end connected between the first and second switches. The control module outputs control signals to control the first and second switches. A second end of the inductance of a first one of the N circuits is connected between two cells of a first pair of 2N series-connected cells of a battery stack. The first and second switches of the first one of the N circuits are connected in parallel to the first pair of 2N series-connected cells.

Abstract: A system including a first plurality of memory cells to store data, and a memory controller to read the first plurality of memory cells and to identify one or more of the first plurality of memory cells in response to the one or more of the first plurality of memory cells being defective. A second plurality of memory cells stores information regarding locations of the one or more of the first plurality of memory cells. The second plurality of memory cells stores the information at a lower density than the first plurality of memory cells. The information read from the second plurality of memory cells has a lower probability of error than the data read from the first plurality of memory cells.

Abstract: A system comprising an interface, a plurality of storage arrays, a data processing module, and a switch module. The interface receives data blocks from a host via a network. The data processing module connected between the interface and the plurality of storage arrays, wherein the data processing module is configured to (i) determine which ones of the data blocks each of a plurality of target processing modules of the storage arrays is to perform error checking and correcting processing, and (ii) transfer each of the data blocks from the interface to a respectively assigned one of the plurality of target processing modules. The switch module provides communication paths between the data processing module and the plurality of storage arrays.

Abstract: A method and system for determining a respective threshold voltage of each of a plurality of transistors in a memory array. The method includes: applying a ramp voltage to gates of the plurality of transistors, wherein the ramp voltage is configured to increase based on an incrementing digital code; as the ramp voltage is being applied, generating a respective control signal in response to sensing a predetermined threshold current along a respective bitline in the memory array, wherein each transistor in the memory array is in communication with a respective bitline in the memory array; and for each transistor in the memory array, latching a current value of the incrementing digital code in response to the respective control signal corresponding to the transistor being generated. The current value of the incrementing digital code latched by each register corresponds to the threshold voltage of the corresponding transistor.

Abstract: A multi-level solid state non-volatile memory array has memory cells that store data using a first number of digital levels. A controller of the memory array encodes a series of data bits to generate a series of encoded data bits, and converts the series of encoded data bits into a series of data symbols. The controller sends, to the memory array, a stored series of data symbols based on the series of data symbols for storage in a memory cell of the multi-level solid state non-volatile memory array. The controller generates an output signal based on data associated with the stored series of data symbols. The output signal is characterized by a second number of digital levels greater than the first number of digital levels. The controller outputs a series of output data symbols based on the output signal.

Abstract: A memory system includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells, and a read/write module. The bit lines include a first bit line and a second bit line. The word lines include a first word line and a second word line. Each memory cell is located at an intersection of a respective one of the bit lines and a respective one of the word lines. The memory cells include a first memory cell and a second memory cell. The first memory cell is located at the intersection of the first bit line and the first word line. The second memory cell is located at the intersection of the second bit line and the second word line. The read/write module is configured to concurrently activate the first memory cell and the second memory cell for (i) a read operation or (ii) a write operation.

Abstract: A read head circuit includes a read element configured to read data stored magnetically on a platter and includes first and second terminals. A write element writes data on the platter. A normally-ON transistor includes first, second and control terminals. The first and second terminals of the transistor are connected to a respective one of the first and second terminals of the read element. The control terminal receives a control voltage referenced from a power terminal. The power terminal powers the read element or the write element. Responsive to the control terminal being powered by the power terminal, the normally-ON transistor provides an open circuit between the first terminal of the read element and the second terminal of the read element. Responsive to the control terminal not being powered by the power terminal, the normally-ON transistor shorts the first and second terminals of the read element.

Abstract: A system includes a first device, a second device, and a main power management module. The first device is configured to communicate with a system bus. The second device is configured to communicate with the system bus. The second device includes a device power management module configured to manage power states of the second device. The main power management module is configured to manage power consumption of the second device independently of the first device by selectively supplying power and clock signals to the second device based on the power states of the second device. The main power management module and the device power management module each comprise a power handshake interface. The main power management module communicates with the device power management module via a power management bus using the power handshake interface.

Abstract: A memory chip including a plurality of storage elements, a receiver and a program module. Each of the storage elements has a measurable parameter. The receiver receives N target values from a memory controller, where N is an integer greater than zero. The programming module adjusts corresponding measurable parameters of N storage elements of the plurality of storage elements to the N target values.

Abstract: A method of providing electrostatic discharge (ESD) protection for a read element in a magnetic storage system comprises coupling a first terminal of a shunting device to a first terminal of the read element; coupling a second terminal of the shunting device to a second terminal of the read element; providing a conductive path between the first and second terminals of the shunting device when the read element is disabled; and providing a nonconductive path between the first and second terminals of the shunting device when the read element is enabled.

Abstract: Devices, systems, methods, and other embodiments associated with monitoring memory are described. In one embodiment, a method determines a first data quality associated with a set of data stored in flash memory. Based, at least in part, on the first data quality, the flash memory is controlled to correct the set of data to produce a corrected set of data. The corrected set of data is reprogrammed into the flash memory.

Abstract: Systems, methods, and other embodiments associated with optimizing the use of replaceable memory cards and onboard memory as storage for data in cache are described. According to one embodiment, an apparatus includes a cache space manager configured to cause a cache processor to store data of a removable memory card of a memory device to an onboard memory of the memory device. The apparatus also includes an error rate monitor configured to monitor operating parameters of the removable memory card and to activate a cache processor to store the data from the removable memory card to the onboard memory when the operating parameters meet predetermined criteria.

Abstract: Methods, systems and computer program products for compensating repeatable timing variations associated with a spindle motor are described. Specifically, a repetitive error correction factor may be determined using a computational model which predicts timing variations. The correction factor can then be used to cancel the effect of the actual timing variations upon the spindle motor.

Abstract: A system includes a first light emitting diode configured to produce light of a first color and a second light emitting diode configured to produce light of a second color. A constant current circuit is configured to provide a first current, wherein (i) the first current is approximately constant, (ii) a first portion of the first current flows through the second light emitting diode, and (iii) a remaining portion of the first current flows through the first light emitting diode. A current regulating circuit is configured to control the first portion of the first current flowing through the second light emitting diode. The current regulating circuit is connected in series with the second light emitting diode, the constant current circuit, and a reference potential. The first light emitting diode is connected in series directly between the constant current circuit and the reference potential.

Abstract: A system including a processor, a first-in first-out (FIFO) module, and an arbiter module. The processor includes i) a processor core and ii) a memory. The FIFO module is configured to receive streaming data, output the streaming data to the memory of the processor, and selectively generate a control signal. The arbiter module is configured to adjust, based on the control signal, a priority in which at least one of the processor core and the FIFO module accesses the memory of the processor.

Abstract: A control module includes an encoder module, which generates a first code word for multiple drives. A detector module, in response to detecting an error in a first drive subsequent to generation of the first code word, initiates replacement of the first drive with a second drive. The encoder module generates a second code word for the second drive. A mapping module maps physical locations of data in the drives to logical locations of the first code word, assigns a predetermined value to one of the logical locations corresponding to the first drive to identify an unused logical location, and assigns the unused logical location to the second drive based on the predetermined value. A difference module generates a third code word based on the first and second code words. The encoder module generates an updated code word for the multiple drives based on the first and third code words.