Abstract: The mapping of High Performance Computing (“HPC”) applications to platforms is provided. An HPC application characterization module determines an HPC application signature to characterize the HPC application. An HPC application mapping module selects a platform from a plurality of platforms to execute the HPC application based on the HPC application signature and a set of benchmarks. An HPC application monitoring module monitors the execution of the HPC application on the selected platform.

Abstract: One example embodiment is a method that simulates a sampling period of an application to collect execution counts of basic blocks and compute cycles per instruction (CPI) data. A non-sampling period of the application is simulated to collect execution counts of basic blocks, and a comparison of the execution counts collected during the sampling period is performed to the execution counts collected during the non-sampling period. Based on the comparison, a determination is made whether to estimate CPI for the basic blocks during the non-sampling period using the CPI data collected during the sampling period.

Abstract: One embodiment is main memory that includes a combination of non-volatile memory (NVM) and dynamic random access memory (DRAM). An operating system migrates data between the NVM and the DRAM.

Abstract: Upon an intermediary device on a network being turned on, controlling system software at the intermediary device is booted such that no public network address is ever assigned to the intermediary device. The intermediary device sends a boot message over the network to central authority software running on one or more first computing devices on the network. The central authority software in response sends messages over the network to the intermediary device and to a second computing device on the network to establish a private tunnel with one another. The intermediary device and the second computing device establish the private tunnel with one another over the network. The intermediary device then opens a remote connection to the second computing device through the private tunnel so that peripherals connected to the intermediary device as if they were directly connected to the second computing device.

Abstract: Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.

Abstract: Nodes interconnected by a network have their substantially parallel execution simulated. Substantially parallel execution of the nodes during a current quantum of simulation time having a quantum length is simulated. Simulation of execution can result in simulation of inter-node data packets being transmitted over the network. When the current quantum of simulation time has elapsed, simulation of execution of the nodes is synchronized. If no inter-node data packets were transmitted in simulation during the current quantum of simulation time, then the quantum length is increased. If one or more inter-node data packets were transmitted in simulation during the current quantum of simulation time, then the quantum length is decreased. This process is then repeated for a next quantum of simulation time having the quantum length as has been increased or decreased.

Abstract: In a method for managing a memory segment through use of a memory virtual appliance, data is encapsulated with the memory virtual appliance, in which the memory virtual appliance comprises a virtual machine configured to manage a memory segment in a physical memory. In addition, the memory virtual appliance is implemented using a virtualization wrapper comprising computer readable code enabling the encapsulated data to be shared among a plurality of clients. Moreover, the encapsulated data is stored in the memory segment controlled by the memory virtual appliance.

Abstract: A memory apparatus (100, 200, 300, 500, 600, 700) has a plurality of memory banks (d0 to d7, m0 to m3, p, p0, p1), wherein a write or erase operation to the memory banks (d0 to d7, m0 to m3, p, p0, p1) is substantially slower than a read operation to the banks (d0 to d7, m0 to m3, p, p0, p1). The memory apparatus (100, 200, 300, 500, 600, 700) is configured to read a redundant storage of data instead of a primary storage location in the memory banks (d0 to d7, m0 to m3, p, p0, p1) for the data or reconstruct requested data in response to a query for the data when the primary storage location is undergoing at least one of a write operation and an erase operation.

Abstract: One example embodiment is a method that simulates a sampling period of an application to collect execution counts of basic blocks and compute cycles per instruction (CPI) data. A non-sampling period of the application is simulated to collect execution counts of basic blocks, and a comparison of the execution counts collected during the sampling period is performed to the execution counts collected during the non-sampling period. Based on the comparison, a determination is made whether to estimate CPI for the basic blocks during the non-sampling period using the CPI data collected during the sampling period.

Abstract: A method for simulating a system normally performs functional simulation of the system without performing timing simulation of the system. The method dynamically samples the functional simulation of the system at intervals to determine whether the functional simulation has entered into a new phase. Where the functional simulation has entered into a new phase, the method performs both the functional simulation and the timing simulation of the system for one or more intervals.

Abstract: One embodiment is main memory that includes a combination of non-volatile memory (NVM) and dynamic random access memory (DRAM). An operating system migrates data between the NVM and the DRAM.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: A method for finding text reading order in a document such as a scanned newspaper or magazine includes the steps of pruning unnecessary text zones using semantic analysis (40), using text correlation measures to cluster zones (41), and then finding a reading order within each of the clusters (42).

Abstract: There is disclosed a data processor that executes variable latency load operations using bypass circuitry that allows load word operations to avoid stalls caused by shifting circuitry.

Abstract: A method and apparatus for producing a document having human-readable content and a position identifying encoding pattern. A printer places text or other content onto a substrate, such as paper, and a filter material application system applies transparent filter material to at least a portion of that content to only modify the reflectivity of the content at a predetermined wavelength. Because the reflectivity of the position identifying encoding pattern remains unchanged, it is distinguishable from the content and can be read at the predetermined wavelength. The position identifying pattern can take a number of forms including a number of dots printed at predetermined positions on the substrate on an imaginary grid.

Abstract: The present invention provides for native execution of an application on a client using code segments transmitted from a server over a network. The server includes an application code source, and a server code segment manager. The server may also include an application code transformation manager if the code source is not in the native binary format of the client. The client includes a client code segment manager, a code cache linker and manager, a code cache, and a CPU. When the client seeks to execute an application, code segments are transmitted from the server to the client and are stored in the code cache. The CPU then executes the code segments natively. When a code segment branches to a segment not in the cache, control passes to the client code segment manager, which requests the needed code segment from the server code segment manager of the server.

Abstract: Upon an intermediary device on a network being turned on, controlling system software at the intermediary device is booted such that no public network address is ever assigned to the intermediary device. The intermediary device sends a boot message over the network to central authority software running on one or more first computing devices on the network. The central authority software in response sends messages over the network to the intermediary device and to a second computing device on the network to establish a private tunnel with one another. The intermediary device and the second computing device establish the private tunnel with one another over the network. The intermediary device then opens a remote connection to the second computing device through the private tunnel so that peripherals connected to the intermediary device as if they were directly connected to the second computing device.

Abstract: Instructions to be executed on a system are simulated. Representative simulation phases of the instructions, which most affect simulation results of the instructions to be executed on the system, are dynamically determined. For each representative simulation phase of the instructions, a model is selected from a number of models that provides specified accuracy with a minimal amount of simulation time, and the representative simulation phase is simulated using the model selected. The simulation results for the instructions to be executed on the system are then output.

Abstract: Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a method of operating the system comprising: loading a first aligned word commencing at an aligned word address rounded from the specified unaligned word address; identifying an index representing the location of the unaligned word address relative to the aligned word address; loading a second aligned word commencing at an aligned word address rounded from a second unaligned word address; and combining indexed portions of the first and second alinged words using the indentified index to construct the unaligned word.

Abstract: A method performs functional simulation of a system as influenced by timing simulation of the system. The method performs functional simulation of a system, and periodically performs timing simulation of the system. The functional simulation of the system takes into account the timing simulation of the system that is periodically performed.