Patents by Inventor Paolo Faraboschi

Paolo Faraboschi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10025663
    Abstract: Local checkpointing using a multi-level call is described herein. An example method includes storing a first datum in a first level of a multi-level cell. A second datum is stored in a second level of the multi-level cell, the second datum representing a checkpoint of the first datum. The first datum is copied from the first level to the second level of the multi-level cell to create the checkpoint.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Doe Hyun Yoon, Robert Schreiber, Paolo Faraboschi, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan
  • Patent number: 9952975
    Abstract: According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 24, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dwight L. Barron, Paolo Faraboschi, Norman P. Jouppi, Michael R. Krause, Sheng Li
  • Publication number: 20180074959
    Abstract: According to an example, a node-based computing device includes memory nodes communicatively coupled to a processor node. The memory nodes may form a main memory address space for the processor node. The processor node may establish a virtual circuit through memory nodes. The virtual circuit may dedicate a path within the memory nodes. The processor node may then communicate a message through the virtual circuit. The memory nodes may forward the message according to the path dedicated by the virtual circuit.
    Type: Application
    Filed: July 22, 2014
    Publication date: March 15, 2018
    Inventors: Sheng Li, Jishen Zhao, Kevin T. Lim, Paolo Faraboschi
  • Publication number: 20180060233
    Abstract: Examples described herein relate to caching in a system with multiple nodes sharing a globally addressable memory. The globally addressable memory includes multiple windows that each include multiple chunks. Each node of a set of the nodes includes a cache that is associated with one of the windows. One of the nodes includes write access to one of the chunks of the window. The other nodes include read access to the chunk. The node with write access further includes a copy of the chunk in its cache and modifies multiple lines of the chunk copy. After a first line of the chunk copy is modified, a notification is sent to the other nodes that the chunk should be marked dirty. After multiple lines are modified, an invalidation message is sent for each of the modified lines of the set of the nodes.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 1, 2018
    Inventors: Gabriel Parmer, Paolo Faraboschi, Dejan S. Milojicic
  • Publication number: 20180025043
    Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.
    Type: Application
    Filed: March 6, 2015
    Publication date: January 25, 2018
    Inventors: Stanko Novakovic, Kimberly Keeton, Paolo Faraboschi, Robert Schreiber
  • Publication number: 20180004674
    Abstract: Examples disclosed herein relate to programmable memory-side cache management. Some examples disclosed herein may include a programmable memory-side cache and a programmable memory-side cache controller. The programmable memory-side cache may locally store data of a system memory. The programmable memory-side cache controller may include programmable processing cores, each of the programmable processing cores configurable by cache configuration codes to manage the programmable memory-side cache for different applications.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Qiong Cai, Paolo Faraboschi
  • Publication number: 20180004456
    Abstract: In one example, a memory network may control access to a shared memory that is by multiple compute nodes. The memory network may control the access to the shared memory by receiving a memory access request originating from an application executing on the multiple compute nodes and determining a priority for processing the memory access request. The priority determined by the memory network may correspond to a memory address range in the memory that is specifically used by the application.
    Type: Application
    Filed: January 30, 2015
    Publication date: January 4, 2018
    Inventors: Vanish Talwar, Paolo Faraboschi, Daniel Gmach, Yuan Chen, Al Davis, Adit Madan
  • Publication number: 20170371561
    Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: Qiong Cai, Paolo Faraboschi, Cong Xu, Ping Chi, Sai Rahul Chalamalasetti, Andrew C. Walton
  • Publication number: 20170371663
    Abstract: Example implementations relate to global capabilities transferrable across node boundaries. For example, in an implementation, a switch that routes traffic between a node and global memory may receive an instruction from the node. The switch may recognize that data referenced by the instruction is a global capability, and the switch may process that global capability accordingly.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Dejan S Milojicic, Paolo Faraboschi, Chris I Dalton
  • Patent number: 9823986
    Abstract: According to an example, a resiliency group for a memory node in a memory network can provide error correction for a memory access in the memory node. The memory access may be received from a main memory controller of a processor connected to the memory network. The memory access may be executed by a memory controller of the memory node.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: November 21, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sheng Li, Norman Paul Jouppi, Paolo Faraboschi, Doe Hyun Yoon, Dwight L. Barron
  • Patent number: 9792182
    Abstract: A technique includes generating a checkpoint for an application that is executing on a plurality of nodes of a distributed computing system. Forming the checkpoint includes selectively regulating communication of data from the plurality of nodes to a storage subsystem based at least in part on a replication of the data among the nodes.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: October 17, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sudarsun Kannan, Paolo Faraboschi, Moray McLaren, Dejan S. Milojicic, Robert Schreiber
  • Publication number: 20170220488
    Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.
    Type: Application
    Filed: March 6, 2015
    Publication date: August 3, 2017
    Inventors: Rajeev Balasubramonian, Naveen Muralimanohar, Gregg B. Lesartre, Paolo Faraboschi, Jishen Zhao
  • Publication number: 20170220256
    Abstract: Techniques for retrieving data blocks from memory devices are provided. In one aspect, a request to retrieve a block of data may be received. The block of data may be in a line in a rank of memory. The rank of memory may include multiple devices. The devices used to store the line in the rank of memory may be determined. The determined devices may be read.
    Type: Application
    Filed: April 30, 2015
    Publication date: August 3, 2017
    Inventors: Rajeev Balasubramonian, Paolo Faraboschi, Gregg B. Lesartre, Naveen Muralimanohar
  • Publication number: 20170220257
    Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.
    Type: Application
    Filed: March 12, 2015
    Publication date: August 3, 2017
    Inventors: Rajeev Balasubramonian, Gregg B. Lesartre, Robert Schreiber, Jishen Zhao, Naveen Muralimanohar, Paolo Faraboschi
  • Publication number: 20170220483
    Abstract: Apertures of a first size in a first physical address space of at least one processor are mapped to respective blocks of the first size in a second address space of a storage medium. Apertures of a second size in the first physical address space are mapped to respective blocks of the second size in the second address space, the second size being different from the first size.
    Type: Application
    Filed: April 30, 2015
    Publication date: August 3, 2017
    Inventors: Mark Lillibridge, Paolo Faraboschi
  • Patent number: 9614728
    Abstract: Examples of the present disclosure include methods, devices, and/or systems. Identifying network communication patterns can include analyzing a distributed computer program of a network, estimating virtual network communication traffic based on the analysis, and mapping the virtual network communication traffic to a physical network link. Identifying network communications patterns can also include identifying the network communication pattern and categorizing the physical communication network link based on an estimated communication intensity of the mapped communication traffic and the network communication pattern. Identifying network communication patterns can further include optimizing an energy used by the network based on the categorization.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 4, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Paolo Faraboschi, Moray McLaren, Dejan S. Milojicic, Robert Schreiber
  • Publication number: 20170046395
    Abstract: A bit vector for a Bloom filter is determined by performing one or more hash function operations on a set of ternary content addressable memory (TCAM) words. A TCAM array is partitioned into a first portion to store the bit vector for the Bloom filter and a second portion to store the set of TCAM words. The TCAM array can be searched using a search word by performing the one or more hash function operations on the search word to generate a hashed search word and determining whether bits at specified positions of the hashed search word match bits at corresponding positions of the bit vector stored in the first portion of the TCAM array before searching the second portion of the TCAM array with the search word.
    Type: Application
    Filed: April 30, 2014
    Publication date: February 16, 2017
    Inventors: Sheng Li, Kevin T. Lim, Dejan S. Milojicic, Paolo Faraboschi
  • Publication number: 20160232379
    Abstract: According to an example, memory integrity checking may include receiving computer program code, and using a loader to load the computer program code in memory. Memory integrity checking may further include verifying the integrity of the computer program code by selectively implementing synchronous verification and/or asynchronous verification. The synchronous verification may be based on loader security features associated with the loading of the computer program code. Further, the asynchronous verification may be based on a media controller associated with the memory containing the computer program code.
    Type: Application
    Filed: October 31, 2013
    Publication date: August 11, 2016
    Inventors: Nigel Edwards, Chris Dalton, Paolo Faraboschi
  • Publication number: 20160173732
    Abstract: A color image is processed into a renderable image. The color image comprises a plurality of pixels. Each pixel has colorimetry defined in a first color space. The renderable image comprises a plurality of renderable pixels defined by a device-vector in a second color space. For each pixel: a device-vector defined in the second color space is selected (301) based on the colorimetry defined in a first color space of the pixel. The device-vector comprises a plurality of elements. Each element includes an identifier and an accumulated weighting. An element of the selected device-vector is reselected (303) until the accumulated weighting (a) is greater than a threshold value (t) associated with the pixel (305). The levels for each color of the second color space (or mappings) for the currently selected (307) element of the selected device-vector is determined (309) to convert the pixel into a renderable pixel.
    Type: Application
    Filed: June 28, 2013
    Publication date: June 16, 2016
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Juan Manuel García Reyero Viñas, Paolo Faraboschi, Jan Morovic, Peter Morovic
  • Publication number: 20160092362
    Abstract: According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.
    Type: Application
    Filed: April 30, 2013
    Publication date: March 31, 2016
    Inventors: Dwight Barron, Paolo Faraboschi, Norman P. Jouppi, Michael R. Krause, Sheng Li