Abstract: A method for simulating a system normally performs functional simulation of the system without performing timing simulation of the system. The method dynamically samples the functional simulation of the system at intervals to determine whether the functional simulation has entered into a new phase. Where the functional simulation has entered into a new phase, the method performs both the functional simulation and the timing simulation of the system for one or more intervals.

Abstract: A method of filling in a form comprising using a digital pen to enter data into data entry areas of the form (64), and providing error feedback to the user (69) contemporaneously with filling in the form, said error feedback being indicative of the user entering a non-allowable entry in said data entry area.

Abstract: Instructions to be executed on a system are simulated. Representative simulation phases of the instructions, which most affect simulation results of the instructions to be executed on the system, are dynamically determined. For each representative simulation phase of the instructions, a model is selected from a number of models that provides specified accuracy with a minimal amount of simulation time, and the representative simulation phase is simulated using the model selected. The simulation results for the instructions to be executed on the system are then output.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address,(ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: An automated document processing system is configured to normalize zones obtained from a document, ant to extract articles from the normalized zones. In one configuration, the system receives at least one zone from the document, and applies at least one zone-breaking factor, thereby creating normalized sub-zones within which text lines are consistent with the at least one zone-breaking factor. The normalized sub-zones may be evaluated to obtain a reading order. Adjacent sub-zones are joined if text similarity exceeds a threshold value. Weakly joined sub-zones are separated where indicated by a topic vectors analysis of the weakly joined sub-zones.

Abstract: A data processor includes execution clusters, an instruction cache, an instruction issue unit, and alignment and dispersal circuitry. Each execution cluster includes an instruction execution pipeline having a number of processing stages, and each execution pipeline is a number of lanes wide. The processing stages execute instruction bundles, where each instruction bundle has one or more syllables. Each lane is capable of receiving one of the syllables of an instruction bundle. The instruction cache includes a number of cache lines. The instruction issue unit receives fetched cache lines and issues complete instruction bundles toward the execution clusters. The alignment and dispersal circuitry receives the complete instruction bundles from the instruction issue unit and routes each received complete instruction bundle to a correct one of the execution clusters. The complete instruction bundles are routed as a function of at least one address bit associated with each complete instruction bundle.

Abstract: A system for analysing and annotating time-varying signals comprises a substrate for carrying the time-varying signal in printed form, a printer for printing the time-varying signal over the substrate and a reading and writing device for reading a local background pattern of the substrate and writing on the substrate, the reading and writing device enabling the position of annotations on the substrate to be determined. Local portions of the background pattern on the substrate uniquely identify a location of the background pattern over the substrate. This enables the position of annotations on the substrate which relate to portions of the signal to be determined. This enables annotations written on the printed plot to be stored digitally. The locations of the markings which define the annotations enable not only the annotations themselves to be recorded, but also the parts of the signal to which they relate.

Abstract: A method of applying content and a data encoding pattern 18 to a product 10 comprises: applying the content 14 to a substrate 12; modifying the reflectivity of the content 14 at a predetermined wavelength; and applying the pattern 18 to the product, wherein the method is such that the pattern can be distinguished from the content at the predetermined wavelength.

Abstract: A method of loading an unaligned word from a specified unaligned word address in a memory, said unaligned word comprising a plurality of indexed portions crossing a word boundary, the method comprising: loading a first aligned word commencing at an aligned word address rounded from said specified unaligned word address; identifying an index representing the location of the unaligned word address relative to the aligned word address; loading a second aligned word commencing at an aligned word address rounded from a second unaligned word address; and combining indexed portions of the first and second aligned words using the identified index to construct the unaligned word.

Abstract: A memory device for use by an electronic appliance has a first data port, a second data port, a data storage portion, and a data allocation device. The first data port is operatively connectable to the electronic appliance. The second data port is operatively connectable to a remote memory device. The data allocation device is operatively connected to the first data port, the second data port, and the data storage portion. The data allocation device is adapted to allocate a portion of memory within the remote memory device for use by the electronic appliance and route data between the first data port, the second data port, and the data storage portion.

Abstract: For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant operands and long constant operands. The constant generator unit extracts the bits of a short constant operand from an instruction syllable and right justifies the bits in an output syllable. For long constant operands, the constant generator unit extracts K low order bits from an instruction syllable and T high order bits from an extension syllable. The right justified K low order bits and the T high order bits are combined to represent the long constant operand in one output syllable. In response to the status of op code bits located within a constant generation instruction, the constant generator unit enables and disables multiplexers to automatically generate the appropriate short or long constant operand.

Abstract: Disclosed herein is a method and apparatus for handling an asynchronous interrupt while emulating software so that the system is in a known state when the interrupt is handled. The method includes suspending the asynchronous interrupt so that it remains pending without interrupting software execution when it arrives, then synchronizing delivery of the interrupt to an instruction by issuing an exception. The instructions which trigger exceptions are inserted in the native code at locations corresponding to original instruction boundaries.

Abstract: There is disclosed a data processor comprising: 1) an instruction execution pipeline comprising N processing stages for executing a load instruction; 2) a status register for storing a modifiable configuration value, the modifiable configuration value having a first value indicating the data processor is capable of executing a misaligned access handling routine and a second value indicating the data processor is not capable of executing a misaligned access handling routine; 3) a misalignment detection circuit for determining if the load instruction performs a misaligned access to a target address of the load instruction and, in response to a determination that the load instruction does perform a misaligned access, generating a misalignment flag; and 4) exception control circuitry capable of detecting the misalignment flag and in response thereto determining if the modifiable configuration value is equal to the first value.

Abstract: A cache flush controller, and an associated method, selectably flushes a memory cache of a data processor. The cache flush controller operates at a memory bus level of the data processor and operates to flush a selected line, or lines of the memory cache by writing arbitrary, selected values to the selected line or lines of the memory cache.

Abstract: Disclosed herein is a method and apparatus for handling an asynchronous interrupt while emulating software so that the system is in a known state when the interrupt is handled. The method includes suspending the asynchronous interrupt so that it remains pending without interrupting software execution when it arrives, then synchronizing delivery of the interrupt to an instruction by issuing an exception. The instructions which trigger exceptions are inserted in the native code at locations corresponding to original instruction boundaries.

Abstract: Apparatus for transforming computer software having a branch operation for conditionally bypassing a memory write operation. The apparatus includes computer executable program code stored in one or more computer readable storage media. The computer executable program code includes code for creating a storage location, code for moving the memory write operation above the branch operation, code for selecting a target address for the memory write operation, wherein the storage location is selected if the branch operation bypasses the memory write operation, and code for replacing an address in the memory write operation with the target address.

Abstract: A memory device for use by an electronic appliance has a first data port, a second data port, a data storage portion, and a data allocation device. The first data port is operatively connectable to the electronic appliance. The second data port is operatively connectable to a remote memory device. The data allocation device is operatively connected to the first data port, the second data port, and the data storage portion. The data allocation device is adapted to allocate a portion of memory within the remote memory device for use by the electronic appliance and route data between the first data port, the second data port, and the data storage portion.

Abstract: Apparatus for dynamically transforming and caching at least one computer program. The apparatus comprises computer executable instructions stored on one or more computer readable storage media. The apparatus includes instructions for dynamically transforming and caching code fragments and for causing the code fragments to be executed by at least one computer processor. The apparatus also includes instructions providing an application programming interface enabling the at least one computer program to activate the instructions for dynamically transforming code fragments and the instructions for caching code fragments.

Abstract: The present invention provides for native execution of an application on a client using code segments transmitted from a server over a network. The server includes an application code source, and a server code segment manager. The server may also include an application code transformation manager if the code source is not in the native binary format of the client. The client includes a client code segment manager, a code cache linker and manager, a code cache, and a CPU. When the client seeks to execute an application, code segments are transmitted from the server to the client and are stored in the code cache. The CPU then executes the code segments natively. When a code segment branches to a segment not in the cache, control passes to the client code segment manager, which requests the needed code segment from the server code segment manager of the server.