Abstract: A method can include receiving network packets including forwarding plane packets; evaluating header information of the network packets to map network packets to any of a plurality of destinations on the module, each destination corresponding to any of a plurality of services executed by offload processors of the module; configuring operations of the offload processors; and in response to forwarding plane packets, executing operations on the forwarding plane packets; wherein the receiving, evaluation and processing of the forwarding plane packets are performed independent of the host processor. Corresponding systems and methods are also disclosed.

Abstract: Various systems and methods are disclosed. One or more of the methods disclosed uses machine learning algorithms to predict biophysical responses from biophysical data, such as heart rate monitor data, food logs, or glucose measurements. Biophysical responses may include behavioral responses. Additional systems and methods extract nutritional information from food items by parsing strings containing names of food items.

Abstract: A server system can include a plurality of servers interconnected by a network. Each server can include a server processor, a socket configured to receive a module, and at least one removable computation module configured for insertion into the socket. Each computation module can include first processing circuits mounted on the computation module and configured to at least decrypt data packets received by the server independent of the server processor and second processing circuits mounted on the computation module and configured to form a virtual switch for switching the data packets.

Abstract: A device can include a server that includes a host processor and at least one hardware acceleration (hwa) module having at least one computing element formed thereon, the at least one computing element including processing circuits configured to execute a plurality of processes, first memory circuits, second memory circuits, and a data transfer fabric configured to enable data transfers between the processing circuits and the first and second memory circuits; wherein the at least one computing element is configured to transfer data to, or receive data from, any of: the processing circuits, the first memory circuits, the second memory circuits, or other computing elements coupled to the data transfer fabric.

Abstract: Various systems and methods are disclosed. One or more of the methods disclosed uses machine learning algorithms to predict biophysical responses from biophysical data, such as heart rate monitor data, food logs, or glucose measurements. Biophysical responses may include behavioral responses. Additional systems and methods extract nutritional information from food items by parsing strings containing names of food items.

Abstract: Various systems and methods are disclosed. One or more of the methods disclosed uses machine learning algorithms to predict biophysical responses from biophysical data, such as heart rate monitor data, food logs, or glucose measurements. Biophysical responses may include behavioral responses. Additional systems and methods extract nutritional information from food items by parsing strings containing names of food items.

Abstract: Various systems and methods are disclosed. One or more of the methods disclosed uses machine learning algorithms to predict biophysical responses from biophysical data, such as heart rate monitor data, food logs, or glucose measurements. Biophysical responses may include behavioral responses. Additional systems and methods extract nutritional information from food items by parsing strings containing names of food items.

Abstract: A network overlay system can include a data transport module having a network interface and a translation module configured to generate offload processing addresses for the network packet data; a system bus; at least one host processor connected to the system bus; and at least one offload processor module coupled to the system bus and configured to receive network packet data associated. Offload processor modules include processing circuits associated with at least one of the offload processing addresses that are configured to encapsulate the network packet data for transport on a logical network or decapsulate the network packet data received from the logical network. The offload processing circuits encapsulate or decapsulate network packet data independent of any host processor.

Abstract: A device can include a server that includes a host processor and at least one hardware acceleration (hwa) module having at least one computing element formed thereon, the at least one computing element including processing circuits configured to execute a plurality of processes, first memory circuits, second memory circuits, and a data transfer fabric configured to enable data transfers between the processing circuits and the first and second memory circuits; wherein the at least one computing element is configured to transfer data to, or receive data from, any of: the processing circuits, the first memory circuits, the second memory circuits, or other computing elements coupled to the data transfer fabric.

Abstract: A system can include a plurality of first server modules interconnected to one another via a communication network, each first server module including a first switch, at least one main processor, and at least one computation module coupled to the main processor by a bus, each computation module including a second switch, and a plurality of computation elements; wherein the second switches of the first server modules form a switching plane for the ingress and egress of network packets independent of any main processors of the first server modules.

Abstract: A distributed computing architecture for executing at least first and second computing operations executed in parallel on a set of data, can include a plurality of servers, including first servers that each include at least one central processing unit (CPU), and at least one offload processing module coupled to CPU by a bus. Each offload processing module can include computation elements. The computation elements can be configured to operate as a virtual switch, and to execute the second computing operations on first processed data to generate second processed data. The virtual switches can form a switch fabric for exchanging data between the offload processing modules. The second computing operations are executed on a plurality of the offload processing modules in parallel.

Abstract: A server system can include a switching tier configured to receive network packets and enable network connections between a plurality of servers and a middle tier comprising first servers of the plurality of servers. Each first server can include at least one host processor, at least one network interface device, and at least one hardware accelerator module physically mounted in the first server. Each hardware accelerator module can include at least one field programmable gate array (FPGA) device coupled to receive network packet data from the switching tier over a first data path, and coupled to the at least one host processor by a second data path, each hardware accelerator module configurable to execute network packet data processing tasks independent from the at least one host processor of the server.

Abstract: A server system can include a plurality of servers interconnected by a network. Each server can include a server processor, a socket configured to receive a module, and at least one removable computation module configured for insertion into the socket. Each computation module can include first processing circuits mounted on the computation module and configured to at least decrypt data packets received by the server independent of the server processor and second processing circuits mounted on the computation module and configured to form a virtual switch for switching the data packets.

Abstract: A system can include a plurality of first server modules interconnected to one another via a communication network, each first server module including a first switch, at least one main processor, and at least one computation module coupled to the main processor by a bus, each computation module including a second switch, and a plurality of computation elements; wherein the second switches of the first server modules form a switching plane for the ingress and egress of network packets independent of any main processors of the first server modules.

Abstract: A distributed computing architecture for executing at least first and second computing operations executed in parallel on a set of data, can include a plurality of servers, including first servers that each include at least one central processing unit (CPU), and at least one offload processing module coupled to CPU by a bus. Each offload processing module can include computation elements. The computation elements can be configured to operate as a virtual switch, and to execute the second computing operations on first processed data to generate second processed data. The virtual switches can form a switch fabric for exchanging data between the offload processing modules. The second computing operations are executed on a plurality of the offload processing modules in parallel.

Abstract: A network overlay system can include a data transport module having a network interface and a translation module configured to generate offload processing addresses for the network packet data; a system bus; at least one host processor connected to the system bus; and at least one offload processor module coupled to the system bus and configured to receive network packet data associated. Offload processor modules include processing circuits associated with at least one of the offload processing addresses that are configured to encapsulate the network packet data for transport on a logical network or decapsulate the network packet data received from the logical network. The offload processing circuits encapsulate or decapsulate network packet data independent of any host processor.

Abstract: A packet handling system is disclosed that can include at least one main processor; a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, the virtual switch configured to receive memory read/write data over the memory bus.

Abstract: A method for handling multiple networked applications using a distributed server system is disclosed. The method can include providing at least one main processor and a plurality of offload processors connected to a memory bus; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch receiving memory read/write data over the memory bus.

Abstract: A structured data processing system is disclosed that can include a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules providing an in-memory database; and a central processing unit (CPU) in the first server connected to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules.

Abstract: A method is disclosed that includes writing data to predetermined physical addresses of a system memory, the data including metadata that identifies a processing type; configuring a processor module to include the predetermined physical addresses, the processor module being physically connected to the memory bus by a memory module connection; and processing the write data according to the processing type with an offload processor mounted on the processor module.