Abstract: A system can include a host processor connected to memory via a system memory bus; and at least one offload processor module, including at least one offload processor mounted on the offload processor module, and configured to execute operations on data received over the system memory bus, and to output context data to memory, and read context data from the memory, and hardware scheduling logic mounted on the module and configured to control operations of the at least one offload processor.

Abstract: A memory bus connected module for providing network overlay services is disclosed. The module comprising can include a memory bus connection, multiple offload processors coupled to the memory bus connection, each offload processor configured to convert incoming packets having a first network protocol to outgoing packets having a second network protocol, and control logic connected to the multiple offload processors for determining order of packet conversion by respective task execution of the multiple offload processors.

Abstract: A context switching cache system is disclosed. The system can include a plurality of offload processors connected to a memory bus, each offload processor having a cache with an associated cache state, a context memory coupled to the offload processors, and a scheduling circuit configured to direct transfer of a cache state between at least one of the offload processors and the context memory.

Abstract: A method for scheduling packet processing is disclosed. The method can include classifying network packets based on session metadata and placing the classified network packets into first multiple input/output queues, with network packets transported to a classification circuit using a memory bus having a defined memory transport protocol, reordering network packets received from the first multiple input/output queues using a scheduling circuit and placing the reordered network packets into a second multiple input/output queues, directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports using an arbitration circuit, and modifying network packets using multiple offload processors, each offload processor coupled to at least one of the multiple output ports, the offload processors configured to direct modified network packets back to the memory bus.

Abstract: A system can include at least one offload processor having a data cache, the offload processor including a slave interface configured to receive write data and provide read data over a memory bus; an offload processor module including context memory and a bus controller connected to the slave interface; and logic coupled to the offload processor and context memory and configured to detect predetermined write operations over the memory bus; wherein the offload processor is configured to execute operations on data received over the memory bus, and to output context data to the context memory, and read context data from the context memory.

Abstract: A method for context switching of multiple offload processors is disclosed. The method can include receiving network packets for processing through a memory bus connected socket, organizing the network packets into multiple sessions for processing, suspending processing of at least one session by reading a cache state of at least one of the offload processor into a context memory by operation of a scheduling circuit, with virtual memory locations and physical cache locations being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing by operation of the scheduling circuit.

Abstract: A memory bus connected module with context switching capability is described. The module can include a memory bus connection compatible with a memory bus socket, a plurality of offload processors attached to the module and connected to a memory bus, with each offload processor having a cache with an associated cache state, a context memory attached to the module and connected to the offload processors, and a scheduling circuit configured to direct a transfer of a cache state between at least one of the offload processors and the context memory.

Abstract: A network overlay system capable of processing network packets having metadata is disclosed. The system can include a data transport module configurable to direct network packets based on network identifier tags, an offload processor module connected to a memory bus and including at least one offload processor capable of modifying segregated network packets, and a memory bus connected between the data transport module and the at least one offload processor to support transport of network packets to the offload processor for modification.

Abstract: A memory bus connected module for scheduling services for network packet processing is disclosed. The module can include a memory bus connection, a scheduling circuit configured to reorder network packets received from the memory bus connection and place the reordered network packets into multiple input/output queues, and multiple offload processors connected to the memory bus connection, each offload processor configured to modify network packets in the multiple input/output queues.

Abstract: A processor module can include an in-line module connector configured to physically connect to an in-line memory slot of a system memory bus; a data interface configured to receive write data from the system memory bus, via the in-line module connector, and according to a predetermined protocol; and at least one offload processor configured to process the write data according to instruction data within the write data; and wherein hardware scheduling logic mounted in the processor module include an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the in-line module and configured to control operations of the at least one offload processor.

Abstract: Method for handling packets are disclosed that can include providing at least one main processor connected to a plurality of offload processors by a memory bus; providing an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; configuring the offload processors to provide security related services on packets prior to redirection to the main processor; operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus; and directing at least some memory read/write data to the arbiter from the virtual switch.

Abstract: A method for handling packets is disclosed. The method can include providing at least one main processor connected to a plurality of offload processors by a memory bus; configuring the offload processors to provide security related services on packets prior to redirection to the main processor; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus.

Abstract: A packet handling system is disclosed that can include at least one main processor, a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter.

Abstract: A method for handling multiple networked applications using a distributed server system is disclosed. The method can include providing at least one main processor and a plurality of offload processors connected to a memory bus; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch receiving memory read/write data over the memory bus.

Abstract: A packet handling system is disclosed that can include at least one main processor; a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, the virtual switch configured to receive memory read/write data over the memory bus.

Abstract: A method is disclosed that includes writing data to predetermined physical addresses of a system memory, the data including metadata that identifies a processing type; configuring a processor module to include the predetermined physical addresses, the processor module being physically connected to the memory bus by a memory module connection; and processing the write data according to the processing type with an offload processor mounted on the processor module.

Abstract: Methods of processing structured data, unstructured data, or both are disclosed. Processing structured data can include providing an in-memory database with at least one of a plurality of modules connected to a memory bus of a server; executing database functions with at least one processor on the module; and directing database queries to the at least one module with a CPU of the server. Processing unstructured data can include executing data processing tasks with a CPU connected to a memory bus; and directing parallel computation tasks to a plurality of modules connected to the memory bus.

Abstract: Methods for handling multiple networked applications using a distributed server system are disclosed. Methods can include providing at least one main processor and a plurality of offload processors connected to a memory bus; providing an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus; and directing at least some memory read/write data to the arbiter from the virtual switch.

Abstract: A system is disclosed that can include at least one processor module connectable to a memory bus. The processor module can include at least one memory, at least one offload processor mounted on the processor module, and configured to execute operations on data received over the memory bus, and to output context data to the memory and read context data from the memory, and a hardware scheduling logic mounted on the module and configured to control operations of the at least one processor.

Abstract: A distributed server system for handling multiple networked applications is disclosed. Systems can include at least one main processor; a plurality of offload processors connected to a memory bus; an arbiter connected to each of the plurality of offload processors, the arbiter configured to schedule resource priority for instructions or data received from the memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter.