Abstract: A structured data processing system is disclosed that can include a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules providing an in-memory database; and a central processing unit (CPU) in the first server connected to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules.

Abstract: A data processing system for unstructured data is disclosed. A plurality of modules can be connected to a memory bus, each including at least one processor. A central processing unit (CPU) can be connected to the modules by the memory bus, with the CPU configured to process computationally intensive data processing tasks while directing parallel computation tasks to a plurality of the modules.

Abstract: Methods of processing structured data are disclosed that can include providing a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules further providing an in-memory database; and connecting a central processing unit (CPU) in the first server to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules.

Abstract: This invention provides a data structure and circuit method for making arbitration decisions between a large number of consumers or parties contending for a resource. The circuit uses a novel data-structure for storing previous decisions of the circuit, so that the delays in circuit decisions are far shorter than logarithmic order, the conventional delay, in the number of consumers.

Abstract: This invention provides a data structure and circuit method to rate limit a scheduler. An admission scheduler is used to identify the times necessary to update the profile information of the flows being scheduled. Rate check and profile check logic transfer flows between the two schedulers. Rate-limited and non-rated limited flows are then scheduled independently.

Abstract: An efficient interval matching circuit configured with an input search-key terminal and an output terminal. The circuit generates a value on the output terminal that uniquely identifies all the intervals matching the input search-key. The circuit's memories are configured using a sub-sampling of interval edges. Interval matching takes place using cascaded matching stages, each with higher precision, until the matching intervals are resolved. Such resolution is independent of the particular search-key presented and of the set of intervals configured.