Abstract: A distributed system server system for providing network overlay services is disclosed. The system can include at least two servers; and a plurality of offload processor modules, each having an input-output (IO) port and multiple offload processors, and including at least a first offload processor module configured to receive and process network packets having a logical identifier, and a second offload processor connected directly to the first offload processor through their respective IO ports, and configured to process at least a portion of the packets having the logical identifier, and returning the processed packets through its IO port.

Abstract: A rack server system for a map/reduce data processing is disclosed. The method can include a plurality of servers arranged in a rack, and a plurality of offload processor modules supported on at least two of the servers, each offload processor module having an input-output (IO) port and multiple offload processors, a first offload processor module configured to execute map steps of the map/reduce data processing, and being connected directly to a second offload processor through their respective IO ports to define a midplane switch, wherein the second offload processor module is configured to execute reduce steps of on data provided from the first offload processor module.

Abstract: An inter-rack server system for a packet processing is disclosed. The system can include a plurality of servers arranged into multiple racks a plurality of top of rack (TOR) units connected to the servers, each TOR unit configured to operate as a TOR switch connecting each of the racks to another of the racks, and a plurality of offload processor modules, each offload processor module having an input-output (IO) port and multiple offload processors, wherein a first offload processor module on a first server on a first rack is connected directly to a second offload processor module on a second server on a second rack, with connection provided through respective IO ports.

Abstract: A distributed system server system for a packet processing without top of rack (TOR) units is disclosed. The system can include a plurality of servers, each having at least one host processor, and a plurality of offload processor modules, each offload processor module having an input-output (IO) port and multiple offload processors, wherein a first offload processor module is connected directly to a second offload processor module through respective IO ports, the first and second offload processors configured to provide bidirectional network packet flow between at least the first and second offload processor modules and at least one host processor without TOR units for an inter-server connection.

Abstract: A rack server system for a packet processing is disclosed. The system can include a plurality of servers mountable in a rack; a top of rack (TOR) unit having connections to each of the servers; and a plurality of offload processor modules, each offload processor module having at least one input-output (IO) port and multiple offload processors, including at least a first offload processor module connected directly to a second offload processor module through their respective IO ports.

Abstract: A system can include a host processor connected to memory via a system memory bus; and at least one offload processor module, including at least one offload processor mounted on the offload processor module, and configured to execute operations on data received over the system memory bus, and to output context data to memory, and read context data from the memory, and hardware scheduling logic mounted on the module and configured to control operations of the at least one offload processor.

Abstract: A method for providing network overlay services using a distributed system server system is disclosed. The method can include providing at least two servers, providing bidirectional network packet flow through input-output (IO) ports of at least two offload processor modules, providing a direct connection between the IO ports of the at least two offload processor modules, and processing network packet data corresponding to a bidirectional network packet flow and a logical identifier with at least one of the offload processor modules.

Abstract: A packet handling system is disclosed that can include at least one main processor, a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter.

Abstract: A method for handling packets is disclosed. The method can include providing at least one main processor connected to a plurality of offload processors by a memory bus; configuring the offload processors to provide security related services on packets prior to redirection to the main processor; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus.

Abstract: A system can include at least one offload processor having a data cache, the offload processor including a slave interface configured to receive write data and provide read data over a memory bus; an offload processor module including context memory and a bus controller connected to the slave interface; and logic coupled to the offload processor and context memory and configured to detect predetermined write operations over the memory bus; wherein the offload processor is configured to execute operations on data received over the memory bus, and to output context data to the context memory, and read context data from the context memory.

Abstract: A distributed server system is disclosed that can handle multiple networked applications. A system can include at least one main processor; a plurality of offload processors connected to a memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch configured to receive memory read/write data over the memory bus.

Abstract: A method for providing network overlay services capable of processing network packets having associated packet metadata is disclosed. The method can include writing packets to a specific memory location accessible by at least one offload processor, with packets transported using a memory bus having a defined memory transport protocol, modifying packet metadata of the packets written to the specific memory location with the at least one offload processor, without requiring modification of the packets by a host processor, and sending the modified packets to the memory bus.

Abstract: A method for processing data is disclosed. The method can include transporting data to a second virtual switch from a first virtual switch using a memory bus having a defined memory transport protocol, writing the transported data to a target memory location, and processing the data written to the target memory location with at least one offload processor included on an offload processor module.

Abstract: A scheduling system for a packet processing system is disclosed. The system can include a classification circuit connected to a memory bus and configurable to classify network packets, placing the classified network packets into first multiple input/output queues, a scheduling circuit for reordering the network packets received from the classification circuit through the first multiple input/output queues and placing the reordered network packets into second multiple input/output queues, an arbitration circuit for directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports, and multiple offload processors, each coupled to at least one of the multiple output ports, the offload processors configured to modify the network packets.

Abstract: A system can include at least one processor module, including an in-line module connector configured to physically connect the processor module to at least one in-line memory slot of a system memory bus; at least one memory; at least one offload processor mounted on the module, and configured to execute operations on data received over the system memory bus, and to output context data to the memory, and read context data from the memory; and hardware scheduling logic including an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the module and configured to control operations of the at least one processor.

Abstract: A method can include receiving write data over a system memory bus via an in-line module connector, the write data including a metadata portion identifying a processing to be performed on at least a portion of the write data; performing the processing on at least a portion of the write data with at least one offload processor mounted on a module having the in-line module connector to generate processed data; and transmitting the processed data over the system memory bus; wherein the system memory bus is further connected to at least one processor connector configured to receive at least one host processor different from the at least one offload processor.

Abstract: An input-output (IO) virtualization system connectable to a network is disclosed. The system can include a second virtual switch connected to a memory bus and configured to receive network packets from a first virtual switch, and an offload processor module supporting the second virtual switch, the offload processor module further comprising at least one offload processor configured to modify network packets and direct the modified network packets to the first virtual switch through the memory bus.

Abstract: A memory bus connected module, connectable to a first virtual switch for providing input-output (IO) virtualization services is disclosed. The module can include a second virtual switch coupled to the first virtual switch via a memory bus connection, a plurality of offload processors coupled to the memory bus connection, and at least one memory unit connected to, and separately addressable by, the multiple offload processors, and configured to receive data directed to a specific memory address space for processing by at least one of the offload processors.

Abstract: A method for context switching of multiple offload processors coupled to receive data for processing over a memory bus is disclosed. The method can include directing storage of a cache state, via a bulk read from a cache of at least one of a plurality of offload processors into a context memory, by operation of a scheduling circuit, with any virtual and physical memory locations of the cache state being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing, by operation of the scheduling circuit.

Abstract: A method for providing scheduling services for network packet processing using a memory bus connected module is disclosed. The method can include transferring network packets to the module through a memory bus connection, reordering network packets received from the memory bus connection with a scheduling circuit and placing the reordered network packets into multiple input/output queues, and modifying reordered network packets placed into multiple input/output queues using multiple offload processors connected to the memory bus.