Patents by Inventor Pascal Fornara

Pascal Fornara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Metallic device having mobile element in a cavity of the BEOL of an integrated circuit
    Patent number: 9875870
    Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: January 23, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Sebastian Orellana
  • EEPROM cell with charge loss
    Patent number: 9874856
    Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: January 23, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Method for generation of electrical power within a three-dimensional integrated structure and corresponding link device
    Patent number: 9847373
    Abstract: Method for generation of electrical power within a three-dimensional integrated structure comprising several elements electrically interconnected by a link device, the method comprising the production of a temperature gradient in at least one region of the link device resulting from the operation of at least one of the said elements, and the production of electrical power using at least one thermo-electric generator comprising at least one assembly of thermocouples electrically connected in series and thermally connected in parallel and contained within the said region subjected to the said temperature gradient.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: December 19, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Prevention of premature breakdown of interline porous dielectrics in an integrated circuit
    Patent number: 9812399
    Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: November 7, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Jean-Philippe Escales
  • CONTROLLABLE INTEGRATED CAPACITIVE DEVICE
    Publication number: 20170309532
    Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventors: Pascal Fornara, Christian Rivero
  • Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuit
    Patent number: 9780045
    Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: October 3, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero, Guilhem Bouton
  • Method of operating an integrated switchable capacitive device
    Patent number: 9754934
    Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • METHOD FOR DETECTING A THINNING OF THE SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK FACE AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20170243652
    Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.
    Type: Application
    Filed: July 25, 2016
    Publication date: August 24, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Controllable integrated capacitive device
    Patent number: 9721858
    Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: August 1, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • METALLIC DEVICE HAVING MOBILE ELEMENT IN A CAVITY OF THE BEOL OF AN INTEGRATED CIRCUIT
    Publication number: 20170207052
    Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Christian Rivero, Pascal Fornara, Sebastian Orellana
  • METHOD FOR FABRICATION OF AN INTEGRATED CIRCUIT RENDERING A REVERSE ENGINEERING OF THE INTEGRATED CIRCUIT MORE DIFFICULT AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20170194267
    Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
    Type: Application
    Filed: March 22, 2017
    Publication date: July 6, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero, Guilhem Bouton
  • Integrated circuit provided with a device for detecting its spatial orientation and/or a modification of this orientation
    Patent number: 9670058
    Abstract: An integrated circuit includes a mechanical device for detection of spatial orientation and/or of change in orientation of the integrated circuit. The device is formed in the BEOL and includes an accommodation whose sides include metal portions formed within various metallization levels. A mobile metal component is accommodated within the accommodation. A monitor inside the accommodation defines a displacement area for the metal component and includes electrically conductive elements disposed at the periphery of the displacement area. The component is configured so as to, under the action of the gravity, come into contact with the two electrically conductive elements in response to a given spatial orientation of the integrated circuit. A detector is configured to detect an electrical link passing through the component and the electrically conductive elements.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 6, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Antonio Di-Giacomo, Pascal Fornara
  • ZENER DIODE HAVING AN ADJUSTABLE BREAKDOWN VOLTAGE
    Publication number: 20170148926
    Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.
    Type: Application
    Filed: January 10, 2017
    Publication date: May 25, 2017
    Inventors: Roberto SIMOLA, Pascal FORNARA
  • Metallic device having mobile element in a cavity of the BEOL of an integrated circuit
    Patent number: 9653392
    Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: May 16, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Sebastian Orellana
  • Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuit
    Patent number: 9640493
    Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: May 2, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero, Guilhem Bouton
  • Method of Operating an Integrated Switchable Capacitive Device
    Publication number: 20170103980
    Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 13, 2017
    Inventors: Pascal Fornara, Christian Rivero
  • PREVENTION OF PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS IN AN INTEGRATED CIRCUIT
    Publication number: 20170098615
    Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.
    Type: Application
    Filed: April 25, 2016
    Publication date: April 6, 2017
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Jean-Philippe Escales
  • Zener diode having an adjustable low breakdown voltage
    Patent number: 9577116
    Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 21, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Roberto Simola, Pascal Fornara
  • Zener diode having an adjustable breakdown voltage
    Patent number: 9577053
    Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 21, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Roberto Simola, Pascal Fornara
  • Method of operating an integrated switchable capacitive device
    Patent number: 9536874
    Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: January 3, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero