Patents by Inventor Paul B. Fischer

Paul B. Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11005447
    Abstract: Embodiments of the invention include microelectronic devices, resonators, and methods of fabricating the microelectronic devices. In one embodiment, a microelectronic device includes a substrate and a plurality of cavities integrated with the substrate. A plurality of vertically oriented resonators are formed with each resonator being positioned in a cavity. Each resonator includes a crystalline or single crystal piezoelectric film.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Paul B. Fischer, Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then
  • Patent number: 10979012
    Abstract: Techniques are disclosed for forming integrated circuit single-flipped resonator devices that include an electrode formed of a two-dimensional electron gas (2DEG). The disclosed resonator devices may be implemented with various group III-nitride (III-N) materials, and in some cases, the 2DEG may be formed at a heterojunction of two epitaxial layers each formed of III-N materials, such as a gallium nitride (GaN) layer and an aluminum nitride (AlN) layer. The 2DEG electrode may be able to achieve similar or increased carrier transport as compared to a resonator device having an electrode formed of metal. Additionally, in some embodiments where AlN is used as the piezoelectric material for the resonator device, the AlN may be epitaxially grown which may provide increased performance as compared to piezoelectric material that is deposited by traditional sputtering techniques.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Bruce A. Block, Paul B. Fischer
  • Publication number: 20210104435
    Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 8, 2021
    Inventors: Il-Seok SON, Colin T. CARVER, Paul B. FISCHER, Patrick MORROW, Kimin JUN
  • Patent number: 10896847
    Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Il-Seok Son, Colin T. Carver, Paul B. Fischer, Patrick Morrow, Kimin Jun
  • Publication number: 20200395358
    Abstract: Disclosed herein are IC structures, packages, and devices that include self-aligned III-N transistors monolithically integrated on the same support structure or material (e.g., a substrate, a die, or a chip) as extended-drain III-N transistors. Self-aligned III-N transistors may provide a viable approach to implementing digital logic circuits, e.g., to implementing enhancement mode transistors, on the same support structure with extended-drain III-N transistors which may be used as high-power transistors used to implement various RF components, thus enabling integration of III-N devices with digital logic.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Johann Christian Rode, Walid M. Hafez
  • Publication number: 20200382099
    Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion having a different resonator thickness. Each wing may also have different thicknesses. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.
    Type: Application
    Filed: August 20, 2020
    Publication date: December 3, 2020
    Applicant: INTEL CORPORATION
    Inventors: Sansaptak Dasgupta, Bruce A. Block, Paul B. Fischer, Han Wui Then, Marko Radosavljevic
  • Publication number: 20200373297
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200373421
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Patent number: 10848127
    Abstract: Techniques are disclosed for forming resonator devices using epitaxially grown piezoelectric films. Given the epitaxy, the films are single crystal or monocrystalline. In some cases, the piezoelectric layer of the resonator device may be an epitaxial III-V layer such as an Aluminum Nitride, Gallium Nitride, or other group III material-nitride (III-N) compound film grown as a part of a single crystal III-V material stack. In an embodiment, the III-V material stack includes, for example, a single crystal AlN layer and a single crystal GaN layer, although any other suitable single crystal piezoelectric materials can be used. An interdigitated transducer (IDT) electrode is provisioned on the piezoelectric layer and defines the operating frequency of the filter. A plurality of the resonator devices can be used to enable filtering specific different frequencies on the same substrate (by varying dimensions of the IDT electrodes).
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 24, 2020
    Assignee: INTEL CORPORATION
    Inventors: Bruce A. Block, Sansaptak Dasgupta, Paul B. Fischer, Han Wui Then, Marko Radosavljevic
  • Publication number: 20200365510
    Abstract: Disclosed herein are peripheral inductors for integrated circuits (ICs), as well as related methods and devices. In some embodiments, an IC device may include a die having an inductor extending around at least a portion of a periphery of the die.
    Type: Application
    Filed: September 20, 2017
    Publication date: November 19, 2020
    Applicant: Intel Corporation
    Inventors: Kevin L. Lin, Paul B. Fischer
  • Patent number: 10840341
    Abstract: A semiconductor device is proposed. The semiconductor device includes a group III-N semiconductor layer, an electrically insulating material layer located on the group III-N semiconductor layer, and a metal contact structure located on the electrically insulating material layer. An electrical resistance between the metal contact structure and the group III-N semiconductor layer through the electrically insulating material layer is smaller than 1*10?7? for an area of 1 mm2. Further, semiconductor devices including a low resistance contact structure, radio frequency devices, and methods for forming semiconductor devices are proposed.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer, Walid M. Hafez
  • Publication number: 20200335590
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Marko Radosavljevic, Sansaptak Dasgupta, Yang Cao, Han Wui Then, Johann Christian Rode, Rahul Ramaswamy, Walid M. Hafez, Paul B. Fischer
  • Publication number: 20200335526
    Abstract: Disclosed herein are IC structures, packages, and devices that include Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si transistors or other non-Si-based devices. In some aspects, the Si-based semiconductor material stack may be provided by semiconductor regrowth over an insulator material. Providing a Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si based devices may provide a viable approach to integrating Si-based transistors with non-Si technologies because the Si-based semiconductor material stack may serve as a foundation for forming Si-based transistors.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Patent number: 10804879
    Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion having a different resonator thickness. Each wing may also have different thicknesses. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Bruce A. Block, Paul B. Fischer, Han Wui Then, Marko Radosavljevic
  • Patent number: 10797139
    Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Kimin Jun, Il-Seok Son, Paul B. Fischer
  • Publication number: 20200312961
    Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N devices, e.g., III-N transistors. In various aspects, TFTs integrated with III-N transistors have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. In various aspects, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Samuel Jack Beach, Xiaojun Weng, Johann Christian Rode, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 10790332
    Abstract: Techniques to fabricate an RF filter using 3 dimensional island integration are described. A donor wafer assembly may have a substrate with a first and second side. A first side of a resonator layer, which may include a plurality of resonator circuits, may be coupled to the first side of the substrate. A weak adhesive layer may be coupled to the second side of the resonator layer, followed by a low-temperature oxide layer and a carrier wafer. A cavity in the first side of the resonator layer may expose an electrode of the first resonator circuit. An RF assembly may have an RF wafer having a first and a second side, where the first side may have an oxide mesa coupled to an oxide layer. A first resonator circuit may be then coupled to the oxide mesa of the first side of the RF wafer.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Paul B. Fischer, Nebil Tanzi, Gregory Chance, Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Publication number: 20200303371
    Abstract: Disclosed herein are integrated circuit structures, packages, and devices that include resistors and/or capacitors which may be provided on the same substrate/die/chip as III-N devices, e.g., III-N transistors. An integrated circuit structure, comprising a base structure comprising a III-N material, the base structure having a conductive region of a doped III-N material. The IC structure further comprises a first contact element, including a first conductive element, a dielectric element, and a second conductive element, wherein the dielectric element is between the first conductive element and the second conductive element, and wherein the first conductive element is between the conductive region and the dielectric element. The IC structure further comprises a second contact element electrically coupled to the first contact element via the conductive region.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Johann Christian Rode, Paul B. Fischer, Walid M. Hafez
  • Publication number: 20200295172
    Abstract: Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.
    Type: Application
    Filed: March 11, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Nidhi Nidhi, Rahul Ramaswamy, Paul B. Fischer, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200294932
    Abstract: IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode