Patents by Inventor Paul B. Fischer

Paul B. Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190287935
    Abstract: Embodiments of the invention include a microelectronic device that includes an insulating substrate, a RF transistor layer, and an interconnect structure disposed on the RF transistor layer. The RF transistor layer includes RF transistors for microwave frequencies. The interconnect structure includes at least one layer of dielectric material and a conductive layer having a plurality of conductive lines. The insulating substrate reduces parasitic capacitances and parasitic coupling to the insulating substrate.
    Type: Application
    Filed: December 21, 2016
    Publication date: September 19, 2019
    Inventors: Paul B. FISCHER, Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA
  • Patent number: 10396045
    Abstract: An apparatus and a system including an apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side and an opposite second side; an inductor disposed on the second side of the structure; and a contact coupled to the inductor and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum including a first side and an opposite second side, wherein the second side is coupled to the substrate; removing a portion of the substrate; forming at least one inductor on the second side of the device stratum; and coupling the at least one inductor to at least one of the plurality of transistor devices.
    Type: Grant
    Filed: September 27, 2015
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Paul B. Fischer
  • Publication number: 20190260342
    Abstract: Embodiments of the invention include microelectronic devices, resonators, and methods of fabricating the microelectronic devices. In one embodiment, a microelectronic device includes a substrate and a plurality of cavities integrated with the substrate. A plurality of vertically oriented resonators are formed with each resonator being positioned in a cavity. Each resonator includes a crystalline or single crystal piezoelectric film.
    Type: Application
    Filed: December 22, 2016
    Publication date: August 22, 2019
    Inventors: Paul B. FISCHER, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Han Wui THEN
  • Patent number: 10367070
    Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Kimin Jun, Il-Seok Son, Paul B. Fischer
  • Publication number: 20190229705
    Abstract: An integrated circuit film bulk acoustic resonator (FBAR) device having multiple resonator thicknesses is formed on a common substrate in a stacked configuration. In an embodiment, a seed layer is deposited on a substrate, and one or more multi-layer stacks are deposited on the seed layer, each multi-layer stack having a first metal layer deposited on a first sacrificial layer, and a second metal layer deposited on a second sacrificial layer. The second sacrificial layer can be removed and the resulting space is filled in with a piezoelectric material, and the first sacrificial layer can be removed to release the piezoelectric material from the substrate and suspend the piezoelectric material above the substrate. More than one multi-layer stack can be added, each having a unique resonant frequency. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 25, 2019
    Applicant: INTEL CORPORATION
    Inventors: SANSAPTAK DASGUPTA, PAUL B. FISCHER, HAN WUI THEN, MARKO RADOSAVLJEVIC
  • Publication number: 20190214965
    Abstract: A bulk acoustic resonator architecture is fabricated by epitaxially forming a piezoelectric film on a top surface of post formed from an underlying substrate. In some cases, the acoustic resonator is fabricated to filter multiple frequencies. In some such cases, the resonator device includes two different resonator structures on a single substrate, each resonator structure configured to filter a desired frequency. Including two different acoustic resonators in a single RF acoustic resonator device enables that single device to filter two different frequencies in a relatively small footprint.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 11, 2019
    Applicant: INTEL CORPORATION
    Inventors: Sansaptak Dasgupta, Bruce A. Block, Paul B. Fischer, Han Wui Then, Marko Radosavljevic
  • Publication number: 20190199322
    Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices that include a bottom electrode formed of a two-dimensional electron gas (2DEG). The disclosed FBAR devices may be implemented with various group III-nitride (III-N) materials, and in some cases, the 2DEG may be formed at a heterojunction of two epitaxial layers each formed of III-N materials, such as a gallium nitride (GaN) layer and an aluminum nitride (AlN) layer. The 2DEG bottom electrode may be able to achieve similar or increased carrier transport as compared to an FBAR device having a bottom electrode formed of metal. Additionally, in some embodiments where AlN is used as the piezoelectric material for the FBAR device, the AlN may be epitaxially grown which may provide increased performance as compared to piezoelectric material that is deposited by traditional sputtering techniques.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 27, 2019
    Applicant: INTEL CORPORATION
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Bruce A. Block, Paul B. Fischer
  • Publication number: 20190199312
    Abstract: Techniques are disclosed for forming integrated circuit single-flipped resonator devices that include an electrode formed of a two-dimensional electron gas (2 DEG). The disclosed resonator devices may be implemented with various group III-nitride (III-N) materials, and in some cases, the 2 DEG may be formed at a heterojunction of two epitaxial layers each formed of III-N materials, such as a gallium nitride (GaN) layer and an aluminum nitride (AlN) layer. The 2 DEG electrode may be able to achieve similar or increased carrier transport as compared to a resonator device having an electrode formed of metal. Additionally, in some embodiments where AlN is used as the piezoelectric material for the resonator device, the AlN may be epitaxially grown which may provide increased performance as compared to piezoelectric material that is deposited by traditional sputtering techniques.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 27, 2019
    Applicant: INTEL CORPORATION
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Bruce A. Block, Paul B. Fischer
  • Publication number: 20190198627
    Abstract: Integrated circuit transistor structures are provided that may reduce capacitive parasitics by using metal on both sides (top and bottom) of a given integrated circuit transistor device layer. For example, in an embodiment, the drain metal interconnect is provided above the transistor device layer, and the source metal interconnect is provided below the transistor layer. Such a configuration reduces the parasitic capacitance not only between the source and drain metal interconnect layers, but also between the neighboring conductors of the drain metal interconnect layer, because the number of pass-thru conductors in the drain metal interconnect layer to access an upper conductor in the source metal interconnect layer is reduced. In other embodiments, the source metal interconnect remains above the transistor device layer, and the drain metal interconnect is moved to below the transistor device layer, to provide similar benefits. Techniques apply equally to any transistor type, including FETs and BJTs.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 27, 2019
    Applicant: INTEL CORPORATION
    Inventors: HAN WUI THEN, SANSAPTAK DASGUPTA, MARKO RADOSAVLJEVIC, PAUL B. FISCHER
  • Publication number: 20190190489
    Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion having a different resonator thickness. Each wing may also have different thicknesses. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: Sansaptak Dasgupta, Bruce A. Block, Paul B. Fischer, Han Wui Then, Marko Radosavljevic
  • Publication number: 20190190488
    Abstract: Techniques are disclosed for forming integrated circuit film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion and having a different resonator thickness. Each wing may also have different thicknesses from one another. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: Sansaptak Dasgupta, Bruce A. Block, Paul B. Fischer, Han Wui Then, Marko Radosavljevic
  • Publication number: 20190189771
    Abstract: Techniques are disclosed for forming Schottky diodes on semipolar planes of group III-nitride (III-N) material structures. A lateral epitaxial overgrowth (LEO) scheme may be used to form the group III-N material structures upon which Schottky diodes can then be formed. The LEO scheme for forming III-N structures may include forming shallow trench isolation (STI) material on a semiconductor substrate, patterning openings in the STI, and growing the III-N material on the semiconductor substrate to form structures that extend through and above the STI openings, for example. A III-N structure may be formed using only a single STI opening, where such a III-N structure may have a triangular prism-like shape above the top plane of the STI layer. Further processing can include forming the gate (e.g., Schottky gate) and tied together source/drain regions on semipolar planes (or sidewalls) of the III-N structure to form a two terminal Schottky diode.
    Type: Application
    Filed: September 28, 2016
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: SANSAPTAK DASGUPTA, MARKO RADOSAVLJEVIC, HAN WUI THEN, PAUL B. FISCHER
  • Publication number: 20190173452
    Abstract: Techniques are disclosed for forming resonator devices using epitaxially grown piezoelectric films. Given the epitaxy, the films are single crystal or monocrystalline. In some cases, the piezoelectric layer of the resonator device may be an epitaxial III-V layer such as an Aluminum Nitride, Gallium Nitride, or other group III material-nitride (III-N) compound film grown as a part of a single crystal III-V material stack. In an embodiment, the III-V material stack includes, for example, a single crystal AlN layer and a single crystal GaN layer, although any other suitable single crystal piezoelectric materials can be used. An interdigitated transducer (IDT) electrode is provisioned on the piezoelectric layer and defines the operating frequency of the filter. A plurality of the resonator devices can be used to enable filtering specific different frequencies on the same substrate (by varying dimensions of the IDT electrodes).
    Type: Application
    Filed: September 30, 2016
    Publication date: June 6, 2019
    Applicant: INTEL CORPORATION
    Inventors: BRUCE A. BLOCK, SANSAPTAK DASGUPTA, PAUL B. FISCHER, HAN WUI THEN, MARKO RADOSAVLJEVIC
  • Patent number: 10236282
    Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Kimin Jun, Il-Seok Son, Rajashree Baskaran, Paul B. Fischer
  • Publication number: 20190057950
    Abstract: An embodiment includes an apparatus comprising: a first device layer included in a top edge of a semiconductor substrate; metal layers, on the first device layer, including first and second metal layers; a second device layer on the metal layers; and additional metal layers on the second device layer; wherein the second device layer is not included in any semiconductor substrate. Other embodiments are described herein.
    Type: Application
    Filed: March 31, 2016
    Publication date: February 21, 2019
    Inventors: Brennen K. Mueller, Patrick Morrow, Paul B. Fischer, Kimin Jun
  • Publication number: 20190006171
    Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.
    Type: Application
    Filed: August 28, 2015
    Publication date: January 3, 2019
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Ravi Pillarisetty, Kimin Jun, Patrick Morrow, Valluri R. Rao, Paul B. Fischer, Robert S. Chau
  • Publication number: 20190006296
    Abstract: An apparatus and a system including an apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side and an opposite second side; an inductor disposed on the second side of the structure; and a contact coupled to the inductor and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum including a first side and an opposite second side, wherein the second side is coupled to the substrate; removing a portion of the substrate; forming at least one inductor on the second side of the device stratum; and coupling the at least one inductor to at least one of the plurality of transistor devices.
    Type: Application
    Filed: September 27, 2015
    Publication date: January 3, 2019
    Inventors: Patrick MORROW, Paul B. FISCHER
  • Publication number: 20180358406
    Abstract: Techniques to fabricate an RF filter using 3 dimensional island integration are described. A donor wafer assembly may have a substrate with a first and second side. A first side of a resonator layer, which may include a plurality of resonator circuits, may be coupled to the first side of the substrate. A weak adhesive layer may be coupled to the second side of the resonator layer, followed by a low-temperature oxide layer and a carrier wafer. A cavity in the first side of the resonator layer may expose an electrode of the first resonator circuit. An RF assembly may have an RF wafer having a first and a second side, where the first side may have an oxide mesa coupled to an oxide layer. A first resonator circuit may be then coupled to the oxide mesa of the first side of the RF wafer.
    Type: Application
    Filed: December 24, 2015
    Publication date: December 13, 2018
    Inventors: Bruce A. BLOCK, Paul B. FISCHER, Nebil TANZI, Gregory CHANCE, Han Wui THEN, Sansaptak DASGUPTA, Marko RADOSAVLJEVIC
  • Publication number: 20180331183
    Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 17, 2015
    Publication date: November 15, 2018
    Inventors: AARON D. LILAK, RISHABH MEHANDRU, HAROLD W. KENNEL, PAUL B. FISCHER, STEPHEN M. CEA
  • Publication number: 20180323174
    Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.
    Type: Application
    Filed: December 23, 2015
    Publication date: November 8, 2018
    Inventors: Brennen K. MUELLER, Patrick MORROW, Kimin JUN, Paul B. FISCHER, Daniel PANTUSO