Patents by Inventor Paul B. Fischer

Paul B. Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180331183
    Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 17, 2015
    Publication date: November 15, 2018
    Inventors: AARON D. LILAK, RISHABH MEHANDRU, HAROLD W. KENNEL, PAUL B. FISCHER, STEPHEN M. CEA
  • Publication number: 20180323174
    Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.
    Type: Application
    Filed: December 23, 2015
    Publication date: November 8, 2018
    Inventors: Brennen K. MUELLER, Patrick MORROW, Kimin JUN, Paul B. FISCHER, Daniel PANTUSO
  • Publication number: 20180248012
    Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
    Type: Application
    Filed: September 24, 2015
    Publication date: August 30, 2018
    Applicant: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Kimin Jun, Il-Seok Son, Paul B. Fischer
  • Publication number: 20180233409
    Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 24, 2015
    Publication date: August 16, 2018
    Inventors: Il-Seok SON, Colin T. CARVER, Paul B. FISCHER, Patrick MORROW, Kimin JUN
  • Publication number: 20180226492
    Abstract: Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 9, 2018
    Inventors: Rishabh MEHANDRU, Patrick MORROW, Paul B. FISCHER, Aaron D. LILAK, Stephen M. CEA
  • Publication number: 20180151541
    Abstract: A method including coupling a device substrate to a carrier substrate; aligning a portion of the device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and after separating the portion of the device substrate, coupling the portion of the device substrate to the host substrate. A method including coupling a device substrate to a carrier substrate with an adhesive between a device side of the device substrate and the carrier substrate; after coupling the device substrate to the carrier substrate, thinning the device substrate; aligning a portion of the thinned device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and coupling the separated portion of the device substrate to the host substrate. An apparatus including a substrate including a submicron thickness and a device layer coupled to a host substrate in a stacked arrangement.
    Type: Application
    Filed: June 26, 2015
    Publication date: May 31, 2018
    Inventors: Kimin JUN, Jacob M. JENSEN, Patrick MORROW, Paul B. FISCHER
  • Patent number: 9921640
    Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Uwe Zillmann, Andre Schaefer, Ruchir Saraswat, Telesphor Kamgaing, Paul B. Fischer, Guido Droege
  • Publication number: 20180045760
    Abstract: Embodiments relate to the formation of test probes. One method includes providing a bulk sheet of an electrically conductive material. A laser is used to cut through the bulk sheet in a predetermined pattern to form a test probe. Other embodiments are described and claimed.
    Type: Application
    Filed: October 26, 2017
    Publication date: February 15, 2018
    Inventors: Roy E. SWART, Paul B. FISCHER, Charlotte C. KWONG
  • Patent number: 9835648
    Abstract: Embodiments of the invention provide methods for forming electrical connections using liquid metals. Electrical connections that employ liquid metals are useful for testing and validation of semiconductor devices. Electrical connections are formed between the probes of a testing interface and the electronic interface of a device under test through a liquid metal region. In embodiments of the invention, liquid metal interconnects are comprised of gallium or liquid metal alloys of gallium. The use of liquid metal contacts does not require a predetermined amount of force be applied in order to reliably make an electrical connection.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Rajashree Baskaran, Kimin Jun, Ting Zhong, Roy E. Swart, Paul B. Fischer
  • Patent number: 9786559
    Abstract: Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: October 10, 2017
    Assignee: INTEL CORPORATION
    Inventors: Paul A. Zimmerman, Scott B. Clendenning, Patricio E. Romero, Paul B. Fischer, Robert Edgeworth
  • Patent number: 9461010
    Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana Andryushchenko, Guanghai Xu
  • Publication number: 20160233206
    Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.
    Type: Application
    Filed: December 18, 2013
    Publication date: August 11, 2016
    Applicant: Intel Corporation
    Inventors: PATRICK MORROW, KIMIN JUN, IL-SEOK SON, RAJASHREE BASKARAN, PAUL B. FISCHER
  • Patent number: 9391447
    Abstract: An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Evan M. Fledell, Paul B. Fischer, Roy E. Swart, Timothy J. Maloney, Jack D. Pippin
  • Publication number: 20160163596
    Abstract: Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages.
    Type: Application
    Filed: February 16, 2016
    Publication date: June 9, 2016
    Applicant: INTEL CORPORATION
    Inventors: Paul A. Zimmerman, Scott B. Clendenning, Patricio E. Romero, Paul B. Fischer, Robert Edgeworth
  • Publication number: 20160133596
    Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.
    Type: Application
    Filed: January 18, 2016
    Publication date: May 12, 2016
    Applicant: Intel Corporation
    Inventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana Andryushchenko, Guanghai Xu
  • Patent number: 9269686
    Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana T. Adryushchenko, Guanghai Xu
  • Publication number: 20160043056
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet is over the interconnect areas of the first and the second die. Conductive vias in the dielectric sheet connect with pads of the interconnect areas. A build-up layer over the dielectric sheet includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias. The dies are mounted to a package substrate through the build-up layers, and a package cover is over the dies, the dielectric sheet, and the build-up layer.
    Type: Application
    Filed: October 19, 2015
    Publication date: February 11, 2016
    Applicant: INTEL CORPORATION
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Patent number: 9177831
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Publication number: 20150091182
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Publication number: 20150008950
    Abstract: Embodiments relate to the formation of test probes. One method includes providing a bulk sheet of an electrically conductive material. A laser is used to cut through the bulk sheet in a predetermined pattern to form a test probe. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2011
    Publication date: January 8, 2015
    Inventors: Roy E. Swart, Paul B. Fischer, Charlotte C. Kwong