Patents by Inventor Paul Chang

Paul Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130238263
    Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
    Type: Application
    Filed: April 22, 2013
    Publication date: September 12, 2013
    Applicant: Mentor Graphics Corporation
    Inventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
  • Publication number: 20130214357
    Abstract: Non-planar Metal Oxide Field Effect Transistors (MOSFETs) and methods for making non-planar MOSFETs with asymmetric, recessed source and drains having improved extrinsic resistance and fringing capacitance. The methods include a fin-last, replacement gate process to form the non-planar MOSFETs and employ a retrograde metal lift-off process to form the asymmetric source/drain recesses. The lift-off process creates one recess which is off-set from a gate structure while a second recess is aligned with the structure. Thus, source/drain asymmetry is achieved by the physical structure of the source/drains, and not merely by ion implantation. The resulting non-planar device has a first channel of a fin contacting a substantially undoped area on the drain side and a doped area on the source side, thus the first channel is asymmetric. A channel on atop surface of a fin is symmetric because it contacts doped areas on both the drain and source sides.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Chung-hsun Lin, Jeffrey W. Sleight
  • Patent number: 8513099
    Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Vijay Narayanan, Jeffrey W. Sleight
  • Publication number: 20130207593
    Abstract: A charging circuit and method for charging a power storage device in a power over Ethernet environment are necessary to prevent unnecessary power consumption. Power sourcing equipment continuously supplies power to a connected device after determining that the device is compatible. In order to prevent supply of power after a power storage device attains full charge, a charging circuit may include an interface for supplying electric power; a sensing circuit including a switch in series with a resistor; and a voltage detection circuit. The voltage detection circuit may communicate with the sensing circuit and may output a first signal that turns the switch OFF when the voltage of the power storage device is greater than or equal to a first voltage and may output a second signal that turns the switch ON when the voltage of the power storage device is less than or equal to a second voltage.
    Type: Application
    Filed: February 13, 2012
    Publication date: August 15, 2013
    Applicant: Cisco Technology, Inc.
    Inventors: Chio Fai Aglaia Kong, Guangmin He, Paul Chang
  • Patent number: 8492748
    Abstract: A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Philip S. Waggoner
  • Publication number: 20130175623
    Abstract: Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JOSEPHINE B. CHANG, PAUL CHANG, MICHAEL A. GUILLORN, CHUNG-HSUN LIN, JEFFREY W. SLEIGHT
  • Publication number: 20130175624
    Abstract: Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.
    Type: Application
    Filed: September 12, 2012
    Publication date: July 11, 2013
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8472239
    Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
  • Publication number: 20130156776
    Abstract: The invention provides methods for treating or decreasing the likelihood of developing a stress-granule related disorder and/or cancer by administering one or more poly-ADP-ribose polymerase (PARP) inhibitors, one or more PARP activators, one or more poly-ADP-ribose glycosylase (PARG) activators, and/or one or more poly-ADP-ribose glycohydrolase ARH3 activators. The invention also provides corresponding methods of decreasing stress granule formation and/or proliferation in a cell or a population of cells. The invention further provides methods of increasing the number of stress granules and proliferation in a cell or a population of cells by administering one or more PARP activators, one or more PARP inhibitors, one or more PARG inhibitors, and/or one or more ARH3 inhibitors.
    Type: Application
    Filed: March 30, 2012
    Publication date: June 20, 2013
    Applicant: Massachusetts Institute of Technology
    Inventors: Paul Chang, Sejal . Vyas, Anthony Leung, Phillip A. Sharp
  • Patent number: 8466451
    Abstract: A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
    Type: Grant
    Filed: December 11, 2011
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
  • Patent number: 8456226
    Abstract: Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: June 4, 2013
    Assignee: Broadcom Corporation
    Inventors: Stephen Chi-Wang Au, Arya Behzad, Paul Chang
  • Patent number: 8435961
    Abstract: The invention provides methods for increasing the activity of an inhibitory RNA (RNAi) in a subject requiring administering one or more poly-ADP-ribose polymerase (PARP) inhibitors and/or one or more PARG activators to the subject. The invention also provides methods for increasing the activity of an inhibitory RNA in a cell or cell population requiring contacting a cell or cell population with one or more PARP inhibitors and/or one or more PARG activators. The invention further provides compositions and kits containing one or more PARP inhibitors and/or one or more PARG activators.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: May 7, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Paul Chang, Anthony Leung, Phillip A. Sharp
  • Patent number: 8429576
    Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: April 23, 2013
    Assignee: Mentor Graphics Corporation
    Inventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
  • Patent number: 8422273
    Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
  • Publication number: 20130062709
    Abstract: Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 14, 2013
    Applicant: International Business Machines Corporation
    Inventors: Paul Chang, Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight
  • Patent number: 8395220
    Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
  • Publication number: 20130004256
    Abstract: A milling machine has a base, a work platform mounted movably on the base, and a ruler mounted on the work platform. The work platform is movable relative to a base axis. The thermal compensation system includes a sensor and a control unit. The sensor is configured to be mounted on the base for sensing a position of each of the work platform and the ruler relative to the base axis. The control unit is coupled to the sensor, and determines a work platform displacement and a ruler displacement according to the positions sensed by the sensor. The control unit further calculates a compensation value based on the work platform displacement and the ruler displacement. The control unit is configured to correct the position of the work platform relative to the base axis according to the compensation value.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 3, 2013
    Applicants: The Department of Electrical Engineering, National Chang-Hua University of Education, BUFFALO MACHINERY COMPANY LIMITED
    Inventors: Ching-Wei WU, Ying-Shing SHIAO, Chia-Hui TANG, Yu-Che WANG, Paul CHANG
  • Publication number: 20120326127
    Abstract: A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Philip S. Waggoner
  • Patent number: D686175
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: July 16, 2013
    Assignee: Veeco Instruments Inc.
    Inventors: Alexander I. Gurary, Keng Moy, Paul Chang
  • Patent number: D690671
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: October 1, 2013
    Assignee: Veeco Instruments Inc.
    Inventors: Alexander I. Gurary, Keng Moy, Chenghung Paul Chang