Patents by Inventor Paul Chang
Paul Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110309332Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.Type: ApplicationFiled: June 17, 2010Publication date: December 22, 2011Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Vijay Narayanan, Jeffrey W. Sleight
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Publication number: 20110307846Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: ApplicationFiled: August 24, 2011Publication date: December 15, 2011Applicant: International Business Machines CorporationInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Patent number: 8077439Abstract: Aspects of a method and system for mitigating risk of electrostatic discharge in a system on chip are provided. In this regard, for an IC comprising a plurality of portions electrically isolated from one another within the IC, ESD current may be routed via one or more paths within and/or on a package to which the IC is bonded. The one or more paths may electrically couple two or more of the portions of the IC. The one or more paths may have low impedance at DC and high impedance at one or more frequencies utilized in the integrated circuit. One of the portions of the IC may be a ground plane for RF circuitry. One of the portions of the IC may be a ground plane for digital circuitry. The one or more paths may be fabricated in one or more metal layers of said package.Type: GrantFiled: November 5, 2008Date of Patent: December 13, 2011Assignee: Broadcom CorporationInventors: Hooman Darabi, Ming Wang Sze, Kent Oertle, Paul Chang
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Publication number: 20110279075Abstract: In a method and module for controlling rotation of a motorized spindle driven by a driving unit, a sensing unit senses vibration of the spindle and generates a voltage signal corresponding to the vibration of the spindle. A processing unit receives the voltage signal from the sensing unit, generates an adjusting ratio equal to a reference voltage corresponding to a predetermined vibration level of the spindle by the voltage signal upon detecting that the voltage signal is greater than the reference voltage and is less than a predetermined threshold voltage that is greater than the reference voltage, and outputs a control signal corresponding to the adjusting ratio to the driving unit such that the driving unit reduces a rotation speed of the spindle by the adjusting ratio in response to the control signal from the processing unit.Type: ApplicationFiled: July 29, 2011Publication date: November 17, 2011Applicants: The Department of Electrical Engineering National Chang-Hua University of Education, Buffalo Machinery Company LimitedInventors: Paul Chang, Tsair-Rong Chen, Jeen-Sheen Row, Chin-Sheng Lu
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Patent number: 8051346Abstract: Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data in the ASIC. At least one of the logics either receives data from the SERDES and/or provides data to the SERDES. The example ASIC may also include an embedded fault injection logic (EFIL) to control injection of a fault to a path (e.g., data, control) associated with at least one of the logics. The example ASIC may also include an embedded set of multiplexers (ESOMs) controlled by the EFIL. The ESOMs are controllable by the EFIL to inject a fault signal to the data path.Type: GrantFiled: February 25, 2009Date of Patent: November 1, 2011Assignee: Cisco Technology, Inc.Inventors: Senthil Somasundaram, Jun Qian, Paul Chang, Thomas A. Hamilton
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Patent number: 8042070Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: GrantFiled: October 23, 2007Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Publication number: 20110232425Abstract: A folding tool includes two support plates, a ratchet driver pivotally mounted between the two support plates, a rotation seat rotatably mounted between the two support plates, and a plurality of tips each removably mounted on the rotation seat and each detachably mounted on the ratchet driver. The ratchet driver drives each of the tips to rotate in the operation direction only and idles in the opposite direction so that each of the tips can rotate the screw member in the operation direction successively so as to screw or unscrew the screw member easily and quickly. Thus, when the folding tool is used in a smaller space, each of the tips is driven by the ratchet driver to rotate the screw member in the operation direction successively and to screw or unscrew the screw member easily and quickly.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Inventors: Maan-Jyi Chang, Paul Chang
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Patent number: 8024552Abstract: Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The method simulates a shift instruction that shifts an operand by a shift count. The method identifies a first shift command and a second shift command. The method computes a mask value. The mask value depends on whether the shift count is less than half of the operand size or greater than or equal to half of the operand size. The method uses the mask value to cause one of the first shift command and the second shift command to produce no shift. In some embodiments, the method allows for the shift count to be specified in bytes or in bits.Type: GrantFiled: October 5, 2009Date of Patent: September 20, 2011Assignee: Apple Inc.Inventors: Hyeonkuk Jeong, Paul Chang
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Publication number: 20110223729Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.Type: ApplicationFiled: May 16, 2011Publication date: September 15, 2011Applicant: DIODES, INCORPORATEDInventors: Paul Chang, Geeng-Chuan Chern, Prognyan Ghosh, Wayne Y.W. Hsueh, Vladmir Rodov
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Patent number: 7964933Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.Type: GrantFiled: June 22, 2007Date of Patent: June 21, 2011Assignee: Diodes Inc.Inventors: Paul Chang, Geeng-Chuan Chern, Prognyan Ghosh, Wayne Y. W. Hsueh, Vladimir Rodov
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Publication number: 20110097329Abstract: The invention provides methods for treating or decreasing the likelihood of developing a stress-granule related disorder and/or cancer by administering one or more poly-ADP-ribose polymerase (PARP) inhibitors, one or more PARP activators, one or more poly-ADP-ribose glycosylase (PARG) activators, and/or one or more poly-ADP-ribose glycohydrolase ARH3 activators. The invention also provides corresponding methods of decreasing stress granule formation and/or proliferation in a cell or a population of cells. The invention further provides methods of increasing the number of stress granules and proliferation in a cell or a population of cells by administering one or more PARP activators, one or more PARP inhibitors, one or more PARG inhibitors, and/or one or more ARH3 inhibitors.Type: ApplicationFiled: June 24, 2010Publication date: April 28, 2011Applicant: Massachusetts Institute of TechnologyInventors: Paul Chang, Sejal Vyas, Anthony Leung, Phillip A. Sharp
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Publication number: 20110097328Abstract: The invention provides methods for increasing the activity of an inhibitory RNA (RNAi) in a subject requiring administering one or more poly-ADP-ribose polymerase (PARP) inhibitors and/or one or more PARG activators to the subject. The invention also provides methods for increasing the activity of an inhibitory RNA in a cell or cell population requiring contacting a cell or cell population with one or more PARP inhibitors and/or one or more PARG activators. The invention further provides compositions and kits containing one or more PARP inhibitors and/or one or more PARG activators.Type: ApplicationFiled: June 23, 2010Publication date: April 28, 2011Applicant: Massachusetts Institute of TechnologyInventors: Paul Chang, Anthony Leung, Phillip A. Sharp
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Publication number: 20110082680Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.Type: ApplicationFiled: October 6, 2009Publication date: April 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Chang, Jie Deng, Terrence B. Hook, Sim Y. Loo, Anda C. Mocuta, Jae-Eun Park, Kern Rim, Xiaojun Yu
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Patent number: 7893492Abstract: A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.Type: GrantFiled: February 17, 2009Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Josephine B. Chang, Paul Chang, Michael A. Guillorn, Jeffrey W. Sleight
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Patent number: 7892945Abstract: A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.Type: GrantFiled: August 2, 2010Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Josephine B. Chang, Paul Chang, Michael A. Guillorn, Jeffrey W. Sleight
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Publication number: 20110031473Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.Type: ApplicationFiled: August 6, 2009Publication date: February 10, 2011Applicant: International Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
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Publication number: 20100330583Abstract: The invention provides nucleic acids encoding PARP fusion proteins, PARP fusion proteins, antibodies that bind to one or more of these PARP fusion proteins, and transgenic cells expressing one or more PARP fusion proteins. The invention also provides methods for identifying an agent as a specific PARP inhibitor or activator requiring contacting one or more PARP fusion proteins with a labeled nicotinamide adenine dinucleotide substrate and the agent and measuring the amount of labeled of ADP-ribose covalently attached to the one or more PARP fusion proteins. The invention also provides methods for identifying an agent that specifically binds to one or more PARP fusion proteins and methods for quantitating the level of one or more PARP proteins in a sample.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Applicant: Massachusetts Institute of TechnologyInventors: Paul Chang, Sejal Vyas
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Publication number: 20100295022Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.Type: ApplicationFiled: May 21, 2009Publication date: November 25, 2010Applicant: International Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A Guillorn, Jeffrey Sleight
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Publication number: 20100295021Abstract: Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.Type: ApplicationFiled: May 21, 2009Publication date: November 25, 2010Applicant: International Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
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Publication number: 20100297816Abstract: A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.Type: ApplicationFiled: August 2, 2010Publication date: November 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Josephine B. Chang, Paul Chang, Michael A. Guillorn, Jeffrey W. Sleight