Patents by Inventor Paul D. Hurwitz
Paul D. Hurwitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955555Abstract: A field effect transistor (FET) includes an active region including a source region, a drain region, and a channel region. The channel region is under a gate and situated between the source region and the drain region. A field region is next to the active region. The channel region has an interface with the field region. The gate has a wide outer gate segment proximate to the interface and a narrow inner gate segment distant from the interface. The wide outer gate segment produces an outer channel length greater than an inner channel length that is produced from the narrow inner gate segment, thereby reducing a leakage current of the FET during an OFF state.Type: GrantFiled: June 6, 2022Date of Patent: April 9, 2024Assignee: Newport Fab, LLCInventors: Rula Badarneh, Roda Kanawati, Kurt Moen, Paul D. Hurwitz
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Publication number: 20230395722Abstract: A field effect transistor (FET) includes an active region including a source region, a drain region, and a channel region. The channel region is under a gate and situated between the source region and the drain region. A field region is next to the active region. The channel region has an interface with the field region. The gate has a wide outer gate segment proximate to the interface and a narrow inner gate segment distant from the interface. The wide outer gate segment produces an outer channel length greater than an inner channel length that is produced from the narrow inner gate segment, thereby reducing a leakage current of the FET during an OFF state.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Inventors: Rula BADARNEH, Roda Kanawati, Kurt Moen, Paul D. Hurwitz
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Patent number: 11756823Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.Type: GrantFiled: July 13, 2022Date of Patent: September 12, 2023Assignee: Newport Fab, LLCInventors: Allan K Calvo, Paul D Hurwitz, Roda Kanawati
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Publication number: 20230128785Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.Type: ApplicationFiled: December 21, 2022Publication date: April 27, 2023Inventors: Allan K. Calvo, Paul D. Hurwitz, Roda Kanawati
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Patent number: 11581215Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.Type: GrantFiled: July 14, 2020Date of Patent: February 14, 2023Assignee: Newport Fab, LLCInventors: Allan K Calvo, Paul D Hurwitz, Roda Kanawati
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Publication number: 20220352007Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.Type: ApplicationFiled: July 13, 2022Publication date: November 3, 2022Inventors: Allan K. Calvo, Paul D. Hurwitz, Roda Kanawati
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Publication number: 20220020633Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.Type: ApplicationFiled: July 14, 2020Publication date: January 20, 2022Inventors: Allan K. Calvo, Paul D. Hurwitz, Roda Kanawati
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Patent number: 11195920Abstract: A semiconductor structure includes a porous semiconductor segment adjacent to a first region of a substrate, and a crystalline epitaxial layer situated over the porous semiconductor segment and over the first region of the substrate. A first semiconductor device is situated in the crystalline epitaxial layer over the porous semiconductor segment. The first region of the substrate has a first dielectric constant, and the porous semiconductor segment has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor segment reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer over the first region of the substrate, and an electrical isolation region separating the first and second semiconductor devices.Type: GrantFiled: October 10, 2019Date of Patent: December 7, 2021Assignee: Newport Fab, LLCInventors: Paul D. Hurwitz, Edward Preisler, David J. Howard, Marco Racanelli
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Publication number: 20210375618Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Inventors: Paul D. Hurwitz, Edward Preisler, David J. Howard, Marco Racanelli
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Patent number: 11164892Abstract: A semiconductor-on-insulator (SOI) device including a handle wafer, a buried oxide (BOX), and a top device layer is provided. A plurality of elongated trenches are formed in the handle wafer. Air gaps are formed in the elongated trenches by pinching off each of the elongated trenches. In one approach, prior to the pinching off, a plurality of lateral openings are formed contiguous with the elongated trenches and adjacent to the BOX. The elongated trenches and/or the lateral openings reduce parasitic capacitance between the handle wafer and the top device layer. In another approach, sidewalls of the elongated trenches are implant-damaged so as to further reduce the parasitic capacitance between the handle wafer and the top device layer.Type: GrantFiled: July 1, 2019Date of Patent: November 2, 2021Assignee: Newport Fab, LLCInventor: Paul D. Hurwitz
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Patent number: 11164740Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.Type: GrantFiled: October 9, 2019Date of Patent: November 2, 2021Assignee: Newport Fab, LLCInventors: Paul D. Hurwitz, Edward Preisler, David J. Howard, Marco Racanelli
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Patent number: 11031555Abstract: A radio frequency (RF) switching circuit includes stacked phase-change material (PCM) RF switches. Each of the PCM RF switches includes a PCM, a heating element transverse to the PCM, and first and second heating element contacts. The first heating element contact is coupled to an RF ground, and the second heating element contact may also be coupled to an RF ground. Each of the PCM RF switches can also include first and second PCM contacts. A compensation capacitor can be coupled across the first and second PCM contacts in at least one of the PCM RF switches.Type: GrantFiled: June 23, 2020Date of Patent: June 8, 2021Assignee: Newport Fab, LLCInventors: Nabil El-Hinnawy, Gregory P. Slovin, Chris Masse, Paul D. Hurwitz, David J. Howard
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Patent number: 10991631Abstract: A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.Type: GrantFiled: July 2, 2018Date of Patent: April 27, 2021Assignee: Newport Fab, LLCInventors: Edward J. Preisler, Paul D. Hurwitz, Marco Racanelli, David J. Howard
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Publication number: 20210111249Abstract: A semiconductor structure includes a porous semiconductor segment adjacent to a first region of a substrate, and a crystalline epitaxial layer situated over the porous semiconductor segment and over the first region of the substrate. A first semiconductor device is situated in the crystalline epitaxial layer over the porous semiconductor segment. The first region of the substrate has a first dielectric constant, and the porous semiconductor segment has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor segment reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer over the first region of the substrate, and an electrical isolation region separating the first and second semiconductor devices.Type: ApplicationFiled: October 10, 2019Publication date: April 15, 2021Inventors: Paul D. Hurwitz, Edward Preisler, David J. Howard, Marco Racanelli
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Publication number: 20210111019Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.Type: ApplicationFiled: October 9, 2019Publication date: April 15, 2021Inventors: Paul D. Hurwitz, Edward Preisler, David J. Howard, Marco Racanelli
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Patent number: 10916585Abstract: A radio frequency (RF) switching circuit includes stacked phase-change material (PCM) RF switches. The stacked PCM RF switches can include a high shunt capacitance PCM RF switch having its heating element contacts near its PCM contacts, and a low shunt capacitance PCM RF switch having its heating element contacts far from its PCM contacts. An RF voltage is substantially uniformly distributed between the high shunt capacitance PCM RF switch and the low shunt capacitance PCM RF switch. The stacked PCM RF switches can also include a wide heating element PCM RF switch having a large PCM active segment, and a narrow heating element PCM RF switch having a small PCM active segment. The wide heating element PCM RF switch will have a higher breakdown voltage than the narrow heating element PCM RF switch.Type: GrantFiled: November 13, 2018Date of Patent: February 9, 2021Assignee: Newport Fab, LLCInventors: Nabil El-Hinnawy, Paul D. Hurwitz, Gregory P. Slovin, Jefferson E. Rose, Roda Kanawati, David J. Howard
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Publication number: 20210005630Abstract: A semiconductor-on-insulator (SOI) device including a handle wafer, a buried oxide (BOX), and a top device layer is provided. A plurality of elongated trenches are formed in the handle wafer. Air gaps are formed in the elongated trenches by pinching off each of the elongated trenches. In one approach, prior to the pinching off, a plurality of lateral openings are formed contiguous with the elongated trenches and adjacent to the BOX. The elongated trenches and/or the lateral openings reduce parasitic capacitance between the handle wafer and the top device layer. In another approach, sidewalls of the elongated trenches are implant-damaged so as to further reduce the parasitic capacitance between the handle wafer and the top device layer.Type: ApplicationFiled: July 1, 2019Publication date: January 7, 2021Inventor: Paul D. Hurwitz
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Publication number: 20200335697Abstract: A radio frequency (RF) switching circuit includes stacked phase-change material (PCM) RF switches. Each of the PCM RF switches includes a PCM, a heating element transverse to the PCM, and first and second heating element contacts. The first heating element contact is coupled to an RF ground, and the second heating element contact may also be coupled to an RF ground. Each of the PCM RF switches can also include first and second PCM contacts. A compensation capacitor can be coupled across the first and second PCM contacts in at least one of the PCM RIF switches.Type: ApplicationFiled: June 23, 2020Publication date: October 22, 2020Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Chris Masse, Paul D. Hurwitz, David J. Howard
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Patent number: 10686486Abstract: A radio frequency (RF) transistor includes a drain, a source, and a gate. A first dielectric having a first dielectric constant is over the source and the drain. A gap is in the first dielectric and over the gate, the gap extending to the gate. A second dielectric is situated in the gap. The second dielectric has a second dielectric constant substantially less than the first dielectric constant so as to reduce a COFF of the RF transistor. The RF transistor can be part of a stack of RF transistors in an RF switch. The RF switch can be situated between an antenna and an amplifier.Type: GrantFiled: July 2, 2019Date of Patent: June 16, 2020Assignee: Newport Fab, LLCInventors: Roda Kanawati, Paul D. Hurwitz
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Patent number: 10622262Abstract: A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.Type: GrantFiled: October 6, 2017Date of Patent: April 14, 2020Assignee: Newport Fab LLCInventors: Edward J. Preisler, Paul D. Hurwitz, Marco Racanelli, David J. Howard