Abstract: A structure includes channel regions located between source/drain regions, and a polysilicon gate structure including a plurality of gate fingers, each extending over a corresponding channel region. Each gate finger includes first and second rectangular portions extending in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along a second axis. This offset causes each source/drain region to have a first section with a first length along the second axis, and a second section with a second length along the second axis, greater than the first length. A single column of contacts having a first width along the second axis is provided in the first section of each source/drain region, and a single column of contacts having a second width along the second axis, greater than the first width, is provided in the second section of each source/drain region.

Abstract: An RF switch includes series-connected transistors having different threshold voltages, breakdown voltages and on-resistances, without relying on different channel lengths to provide these differences. A first set of transistors located near a power amplifier output are fabricated to have first channel regions with relatively high dopant concentrations. A second set of transistors located near an antenna input, are fabricated to have second channel regions with relatively low dopant concentrations. The first set of transistors can also include halo implants to increase the dopant concentrations in the first channel regions. Lightly doped drain (LDD) regions of the first set of transistors can have a lower dopant concentration (and be shallower) than LDD regions of the second set of transistors. Transistors in the first set have a relatively high on-resistance, a relatively high breakdown voltage and a relatively high threshold voltage, when compared with transistors in the second set.

Abstract: A radio frequency (RF) switching circuit includes stacked phase-change material (PCM) RF switches. The stacked PCM RF switches can include a high shunt capacitance PCM RF switch having its heating element contacts near its PCM contacts, and a low shunt capacitance PCM RF switch having its heating element contacts far from its PCM contacts. An RF voltage is substantially uniformly distributed between the high shunt capacitance PCM RF switch and the low shunt capacitance PCM RF switch. The stacked PCM RF switches can also include a wide heating element PCM RF switch having a large PCM active segment, and a narrow heating element PCM RF switch having a small PCM active segment. The wide heating element PCM RF switch will have a higher breakdown voltage than the narrow heating element PCM RF switch.

Abstract: A high power semiconductor switch including a plurality of transistor switch circuits connected in series between first and second ports. A first set of transistor switch circuits is located immediately adjacent to the first port, a second set of transistor switch circuits is located immediately adjacent to the second port, and a third set of transistor switch structures are located between the first and second sets. Each transistor switch circuit of the first and second set includes a switching transistor and a dynamic impedance circuit, wherein the dynamic impedance circuit reduces the effective impedance of the corresponding switching transistor when an RF signal is being transmitted. The dynamic impedance circuits are designed to reduce and equalize the voltage drops across the switching transistors of the first and second sets.

Abstract: A non-linear shunt circuit is coupled in a shunt-type configuration (e.g., parallel to an RF switch shunt branch) between a main signal line and ground in an RF circuit, and includes a harmonic cancellation element (HCE) (e.g., back-to-back diodes or diode-connected FETs) configured to cancel third harmonics generated on the main signal line by operation of an RF switch. The RF switch includes a series branch made up of multiple FETs coupled in series in the main signal line between a transmitter/receiver circuit and an antenna. The HCE is coupled to the main signal line either by way of a mid-point node or an input/output terminal of the RF switch's series branch. The non-linear shunt circuit also includes optional protection circuits that provide frequency-independent impedance through the HCE. Various techniques (e.g., active biasing) are optionally utilized to increase effectiveness to a wider range of the switch input power levels.

Abstract: A structure includes channel regions located between source/drain regions, and a polysilicon gate structure including a plurality of gate fingers, each extending over a corresponding channel region. Each gate finger includes first and second rectangular portions extending in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along a second axis. This offset causes each source/drain region to have a first section with a first length along the second axis, and a second section with a second length along the second axis, greater than the first length. A single column of contacts having a first width along the second axis is provided in the first section of each source/drain region, and a single column of contacts having a second width along the second axis, greater than the first width, is provided in the second section of each source/drain region.

Abstract: Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation and optional deep trench isolation regions are formed through the counter-doped second region, providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

Abstract: Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

Abstract: A semiconductor structure includes a plurality of source/drain regions, a plurality of channel/body regions located between the source/drain regions, and a polysilicon gate structure located over the plurality of channel/body regions. The polysilicon gate structure includes a plurality of polysilicon gate fingers, each extending over a corresponding one of the channel/body regions. Each polysilicon gate finger includes first and second rectangular portions that extend in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along the first axis. This offset results in each source/drain region having a first section with a first length, and a second section with a second length, greater than the first length. A single column of contacts are provided in the first section of each source/drain region, and multiple columns of contacts are provided in the second section of each source/drain region.

Abstract: Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

Abstract: Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation and optional deep trench isolation regions are formed through the counter-doped second region, providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

Abstract: A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.

Abstract: A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.

Abstract: A non-linear shunt circuit is coupled in a shunt-type configuration (e.g., parallel to an RF switch shunt branch) between a main signal line and ground in an RF circuit, and includes a harmonic cancellation element (HCE) (e.g., back-to-back diodes or diode-connected FETs) configured to cancel third harmonics generated on the main signal line by operation of an RF switch. The RF switch includes a series branch made up of multiple FETs coupled in series in the main signal line between a transmitter/receiver circuit and an antenna. The HCE is coupled to the main signal line either by way of a mid-point node or an input/output terminal of the RF switch's series branch. The non-linear shunt circuit also includes optional protection circuits that provide frequency-independent impedance through the HCE. Various techniques (e.g., active biasing) are optionally utilized to increase effectiveness to a wider range of the switch input power levels.

Abstract: Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation (STI) and optional deep trench isolation (DTI) regions are formed through the counter-doped second region, thereby providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.

Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.

Abstract: Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.

Abstract: Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation (STI) and optional deep trench isolation (DTI) regions are formed through the counter-doped second region, thereby providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.