Abstract: An RF switch includes series-connected transistors having different threshold voltages, breakdown voltages and on-resistances, without relying on different channel lengths to provide these differences. A first set of transistors located near a power amplifier output are fabricated to have first channel regions with relatively high dopant concentrations. A second set of transistors located near an antenna input, are fabricated to have second channel regions with relatively low dopant concentrations. The first set of transistors can also include halo implants to increase the dopant concentrations in the first channel regions. Lightly doped drain (LDD) regions of the first set of transistors can have a lower dopant concentration (and be shallower) than LDD regions of the second set of transistors. Transistors in the first set have a relatively high on-resistance, a relatively high breakdown voltage and a relatively high threshold voltage, when compared with transistors in the second set.

Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.

Abstract: Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

Abstract: A radio frequency (RF) switch includes a plurality of silicon-on-insulator (SOI) CMOS transistors. A first metal layer (M1) includes traces that connect the SOI CMOS transistors in series to form the RF switch. The first metal layer has a first metal composition. Additional metal layers, having a second metal composition, are formed over the first metal layer. In one embodiment the first metal composition is copper, and the second metal composition is a primarily aluminum composition. In one embodiment, first metal layer is fabricated using a process node having a first minimum line width, and the additional metal layers are fabricated using a process node having a second minimum line width, greater than the first minimum line width. The first metal layer exhibits a reduced resistance and capacitance, thereby reducing the on-resistance and off-capacitance of the RF switch.

Abstract: Methods for fabricating both PD-SOI devices and FD-SOI devices on the same semiconductor substrate are provided. The methods begin with a SOI wafer having a top silicon layer with a thickness appropriate for the fabrication of PD-SOI devices. During the fabrication process, portions of the top silicon layer, to be used for the fabrication of FD-SOI devices, are selectively thinned, so that a portion of the wafer has a top silicon thickness appropriate for FD-SOI devices. FD-SOI devices (e.g., RF switch transistors) are fabricated in the thinned portions of the top silicon layer, and PD-SOI devices (e.g., control transistors for the RF switch transistors) are fabricated in the non-thinned portions of the top silicon layer. Thus, both PD-SOI and FD-SOI devices can be combined within the same integrated circuit.

Abstract: An RF switch includes series-connected transistors having different threshold voltages, breakdown voltages and on-resistances, without relying on different channel lengths to provide these differences. A first set of transistors located near a power amplifier output are fabricated to have first channel regions with relatively high dopant concentrations. A second set of transistors located near an antenna input, are fabricated to have second channel regions with relatively low dopant concentrations. The first set of transistors can also include halo implants to increase the dopant concentrations in the first channel regions. Lightly doped drain (LDD) regions of the first set of transistors can have a lower dopant concentration (and be shallower) than LDD regions of the second set of transistors. Transistors in the first set have a relatively high on-resistance, a relatively high breakdown voltage and a relatively high threshold voltage, when compared with transistors in the second set.

Abstract: A method of forming a semiconductor structure is disclosed. The method includes forming a semiconductor wafer having a device layer situated over a handle substrate, the device layer having at least one semiconductor device, forming a front side glass on a front side of the semiconductor wafer, and partially removing the handle substrate from a back side of the semiconductor wafer. The method also includes removing a portion of the semiconductor wafer from an outer perimeter thereof, either by sawing an edge trim trench through the handle substrate, the device layer and into the front side glass to form a ring, and removing the ring on the outer perimeter of the semiconductor wafer, or by edge grinding the outer perimeter of the semiconductor wafer. The method further includes completely removing the handle substrate.

Abstract: A structure includes a field isolation region in a high resistivity substrate, a compensation implant region under the field isolation region in the high resistivity substrate, where the compensation implant region is configured to substantially eliminate a parasitic p-n junction under the field isolation region. The parasitic p-n junction is formed between trapped charges in the field isolation region and the high resistivity substrate. The compensation implant region includes a charge of a first conductivity type to compensate a parasitic charge of a second conductivity type under the field isolation region. The compensation implant region is configured to improve linearity of RF signals propagating through a metallization layer over the field isolation region. The structure further includes a deep trench extending through the field isolation region and the compensation implant region, and a damaged region adjacent the deep trench.

Abstract: A hybrid MOS-PCM IC switch utilizes both MOS transistors and groups of parallel-connected Phase-Change Material (PCM) cells to control signal transmissions. The MOS transistors are separated by PCM cell groups, and the PCM cells are configured to generate similar COFF or lower values as the MOS transistors, whereby the hybrid switch is both smaller and exhibits lower FOM than standard CMOS SOI switches. When switched into an open (OFF/high-resistance) state, both the PCM cells and MOS transistors function to distribute high VBSR voltages, and the MOS transistors prevent unintended phase changes (ON/OFF switching) of the PCM cells by preventing exponential current flow. In the closed (ON/conducting) state, the PCM cells facilitate lower total RON, whereby the hybrid CMOS SOI switch achieves improved FOM. The MOS transistors may also function as drivers during programming (switching) of direct-heating-type PCM cells.

Abstract: A radio frequency switch includes a plurality of n-channel SOI CMOS transistors connected in series, wherein each of these transistors has a gate width of at least about 0.13 microns. A contact etch stop layer (CESL) structure having a relatively large thickness of at least about 1000 Angstroms is formed on silicide regions of the n-channel SOI CMOS transistors, wherein the CESL structure places a tensile stress on channel regions of the n-channel SOI CMOS transistors, thereby reducing the on-resistances of the n-channel SOI CMOS transistors. The CESL structure is also formed over p-channel SOI CMOS transistors fabricated on the same substrate as the n-channel SOI CMOS transistors. While the CESL structure also places a tensile stress on channel regions of the p-channel SOI CMOS transistors (increasing the on-resistances of these transistors), the on-resistances of the p-channel SOI CMOS transistors are non-critical in the RF switch application.

Abstract: A radio frequency (RF) switch includes a plurality of silicon-on-insulator (SOI) CMOS transistors. A first metal layer (M1) includes traces that connect the SOI CMOS transistors in series to form the RF switch. The first metal layer has a first metal composition. Additional metal layers, having a second metal composition, are formed over the first metal layer. In one embodiment the first metal composition is copper, and the second metal composition is a primarily aluminum composition. In one embodiment, first metal layer is fabricated using a process node having a first minimum line width, and the additional metal layers are fabricated using a process node having a second minimum line width, greater than the first minimum line width. The first metal layer exhibits a reduced resistance and capacitance, thereby reducing the on-resistance and off-capacitance of the RF switch.

Abstract: A method of forming a semiconductor structure is disclosed. The method includes forming a semiconductor wafer having a device layer situated over a handle substrate, the device layer having at least one semiconductor device, forming a front side glass on a front side of the semiconductor wafer, and partially removing the handle substrate from a back side of the semiconductor wafer. The method also includes removing a portion of the semiconductor wafer from an outer perimeter thereof, either by sawing an edge trim trench through the handle substrate, the device layer and into the front side glass to form a ring, and removing the ring on the outer perimeter of the semiconductor wafer, or by edge grinding the outer perimeter of the semiconductor wafer. The method further includes completely removing the handle substrate.

Abstract: A structure includes a field isolation region in a high resistivity substrate, a compensation implant region under the field isolation region in the high resistivity substrate, where the compensation implant region is configured to substantially eliminate a parasitic p-n junction under the field isolation region. The parasitic p-n junction is formed between trapped charges in the field isolation region and the high resistivity substrate. The compensation implant region includes a charge of a first conductivity type to compensate a parasitic charge of a second conductivity type under the field isolation region. The compensation implant region is configured to improve linearity of RF signals propagating through a metallization layer over the field isolation region. The structure further includes a deep trench extending through the field isolation region and the compensation implant region, and a damaged region adjacent the deep trench.

Abstract: A radio frequency (RF) switch includes a plurality of series-connected silicon-on-insulator (SOI) CMOS transistors fabricated using a 0.13 micron (or larger) process, wherein the SOI CMOS transistors include nickel silicide formed on the source/drain regions. Each of the series-connected SOI CMOS transistors has a gate length of about 0.13 microns or more, thereby enabling these SOI CMOS transistors to handle high power RF signals, and exhibit the high breakdown voltages required to implement an RF switch. The nickel silicide regions advantageously contribute to a relatively a low on-resistance (RON) of the SOI CMOS transistors, while consuming a relatively small amount of the underlying silicon regions during their fabrication. The SOI CMOS transistors can be fabricated on a relatively thin silicon layer, thereby contributing to a relatively low off capacitance (COFF) of the SOI CMOS transistors. As a result, an RON*COFF value of the RF switch is advantageously minimized.

Abstract: Disclosed is a structure for improved electrical signal isolation in a semiconductor substrate between integrated passive devices (IPDs) and an associated method for the structure's fabrication. The structure includes an amorphized region in the semiconductor substrate, a dielectric layer formed over the amorphized region, and IPDs formed over the dielectric layer. The amorphized region is not recrystallized and may be formed by utilizing an inert implant that does not charge-dope the amorphized region, while forming a plurality of charge carrier traps at an interface between the amorphized region and the dielectric layer to prevent a parasitic conduction layer from forming at the interface. The inert implant may include one of Argon, Xenon and Germanium. In many implementations, the structure does not include an active device.

Abstract: Provided is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and a method for the structure's fabrication. The structure comprises a gate situated on the top semiconductor layer, the top semiconductor layer situated over a base oxide layer, and the base oxide layer situated over a handle wafer. The top surface of the handle wafer is amorphized by an inert implant of Xenon or Argon to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.

Abstract: A structure having improved electrical signal isolation and linearity is disclosed. The structure includes a buried oxide (“BOX”) layer over a bulk semiconductor layer, a device layer over the buried oxide layer, a compensation implant region near an interface of the buried oxide layer and the bulk semiconductor layer, wherein the compensation implant region is configured to substantially eliminate a parasitic conduction layer near the buried oxide layer. The compensation implant region has a doping concentration of at least one order of magnitude higher than a doping concentration of the bulk semiconductor layer. The structure includes a deep trench extending through the device layer and the buried oxide layer, and a damaged implant region in the bulk semiconductor layer near the deep trench. The structure also includes at least one transistor in the device layer.

Abstract: A semiconductor device includes a source finger electrode coupled to a source region in a semiconductor die, a drain finger electrode coupled to a drain region in the semiconductor die, where the source finger electrode includes at least one isolated segment and a main segment having a first portion and a second portion narrower than the first portion, whereby the source finger electrode reduces a drain-to-source capacitance of the semiconductor device. A common source rail is electrically coupled to the at least one isolated segment and the main segment of the source finger electrode. The drain finger electrode includes at least one isolated segment and a main segment having a first portion and a second portion narrower than the first portion. A common drain rail is electrically coupled to the at least one isolated segment and the main segment of the drain finger electrode.

Abstract: Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate.

Abstract: An RF switch includes series-connected transistors having different threshold voltages, breakdown voltages and on-resistances, without relying on different channel lengths to provide these differences. A first set of transistors located near a power amplifier output are fabricated to have first channel regions with relatively high dopant concentrations. A second set of transistors located near an antenna input, are fabricated to have second channel regions with relatively low dopant concentrations. The first set of transistors can also include halo implants to increase the dopant concentrations in the first channel regions. Lightly doped drain (LDD) regions of the first set of transistors can have a lower dopant concentration (and be shallower) than LDD regions of the second set of transistors. Transistors in the first set have a relatively high on-resistance, a relatively high breakdown voltage and a relatively high threshold voltage, when compared with transistors in the second set.