Abstract: The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. Various method embodiments relate to forming a magnetic random access memory (MRAM) array. Various embodiments include forming a first wiring layer of approximately parallel conductors, a second wiring layer of approximately parallel conductors and a third wiring layer of approximately parallel conductors such that the first, second and third wiring layers cross at a number of intersections. At least one of the first, second and third wiring layers are formed so as to be non-orthogonal with respect to a remaining at least one of the first, second and third wiring layers. The method further includes forming a layer of magnetic storage elements proximately located to the intersections. Other aspects are provided herein.

Abstract: The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. One aspect of the present subject matter relates to a method for forming non-orthogonal images in a raster-based photolithographic system. According to various embodiments of the method, a first image corresponding to a first data set is formed on a reticle when the reticle is at a first rotational position ?1. The reticle is adjusted to a second rotational position ?2. A second image corresponding to a second data set is formed on the reticle when the reticle is at the second rotational position ?2. The second image is non-orthogonal with respect to the first image. Other aspects are provided herein.

Abstract: Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. The low energy ion implantation allows for the distinct placement of both the diffusion barrier and the seed layer. Structures are formed with a barrier/adhesion layer deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (eV) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. Such structures include aluminum, copper, gold, and silver metal interconnects.

Abstract: An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that the air bridge is suspended above the substrate. The air bridge comprises a highly conductive material, such as silver, so as to provide the air bridge with a reduced resistivity. To inhibit gaseous medium from contaminating the air bridge, the air bridge further comprises an adherent coating interposed between the air bridge and the gaseous medium. A method of forming the electrical interconnect is also disclosed, wherein, prior to forming the adherent coating, the conductive material is processed so as to form fewer grain boundaries, which enhances the electrical properties of the air bridge.

Abstract: The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. One aspect of the present subject matter relates to a method for forming non-orthogonal images in a raster-based photolithographic system. According to various embodiments of the method, a first image corresponding to a first data set is formed on a reticle when the reticle is at a first rotational position ?1. The reticle is adjusted to a second rotational position ?2. A second image corresponding to a second data set is formed on the reticle when the reticle is at the second rotational position ?2. The second image is non-orthogonal with respect to the first image. Other aspects are provided herein.

Abstract: An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that the air bridge is suspended above the substrate. The air bridge comprises a highly conductive material, such as silver, so as to provide the air bridge with a reduced resistivity. To inhibit gaseous medium from contaminating the air bridge, the air bridge further comprises an adherent coating interposed between the air bridge and the gaseous medium. A method of forming the electrical interconnect is also disclosed, wherein, prior to forming the adherent coating, the conductive material is processed so as to form fewer grain boundaries, which enhances the electrical properties of the air bridge.

Abstract: A multichip cube structure having a foamed insulating material disposed between adjacent integrated circuit chips. The foamed insulating material has lower dielectric constant and therefore reduces the capacitive coupling between electrical interconnects on adjacent chips. The foamed insulating material also has higher ductility and lower thermal coefficient of expansion than conventional oxide insulators so as to reduce the occurrence of stress induced cracking in circuitry.

Abstract: A semiconductor die having multiple solder bumps, each having a diameter less than about 100 microns, and the method for making such a die are described. The solder bumps are preferably about 10 microns in diameter, and the pitch between the solder bumps is less than 100 microns, and preferably less than or equal to 10 microns. A thermal solder jet apparatus is utilized to deposit solder material to form the solder bumps. The apparatus includes a print head having a plurality of solder ejection ports. Each ejection port has an associated gas ejection conduit connected to a chamber containing one or more hydride films. The hydride film is heated to disassociate hydrogen gas. The hydrogen gas rapidly builds up in the conduit which leads to the ejection port which is loaded with a solder material and forces the ejection of the solder material from the port.

Abstract: A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a semiconductor structure. The system includes a container to hold at least one semiconductor chip having surfaces to be in contact with a fluid. The system also includes a transducer and a heat exchanger disposed within the container and operably positioned with respect to each other to perform a thermoacoustic cooling process. In this system, the transducer is adapted to generate sound waves within the fluid such that compression and decompression of the fluid provides a temperature gradient across the semiconductor chip to transfer heat from the semiconductor chip to the heat exchanger, and the heat exchanger is adapted to remove heat from the fluid in the container. Other aspects and embodiments are provided herein.

Abstract: An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials act as insulating layers through which trenches and vias are subsequently formed by employing a timed etching. Since the low dielectric constant materials are selected so that the etchant available for each one has only a small etch rate relative to the other low dielectric constant materials, the plurality of low dielectric constant materials act as etch stops during the fabrication of interconnect structures. This way, the etch stop layers employed in the prior art are eliminated and the number of fabrication steps is reduced.

Abstract: A method for assembling semiconductor dice includes orienting at least one second semiconductor die with the active surface thereof facing the active surface of a first semiconductor die. A structure on an active surface of one of the semiconductor dice may interact with a peripheral edge or other feature of another of the semiconductor dice to facilitate alignment of corresponding bond pads of the semiconductor dice. Corresponding bond pads of the first and at least one second semiconductor dice are connected. For example, conductive structures may be formed or placed between the corresponding bond pads. Bond pads of the first semiconductor die that are laterally beyond an outer periphery of each second semiconductor die may be electrically connected to corresponding contacts.

Abstract: Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.

Abstract: An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that the air bridge is suspended above the substrate. The air bridge comprises a highly conductive material, such as silver, so as to provide the air bridge with a reduced resistivity. To inhibit gaseous medium from contaminating the air bridge, the air bridge further comprises an adherent coating interposed between the air bridge and the gaseous medium. A method of forming the electrical interconnect is also disclosed, wherein, prior to forming the adherent coating, the conductive material is processed so as to form fewer grain boundaries, which enhances the electrical properties of the air bridge.

Abstract: A multi-chip electronic package comprised of a plurality of integrated circuit chips secured together in a stack formation. The chip stack is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A process and structure is proposed that allows for densely-packed, multi-chip electronic packages to be manufactured with improved heat dissipation efficiency, thus improving the performance and reliability of the multi-chip electronic package.

Abstract: A semiconductor die having multiple solder bumps, each having a diameter less than about 100 microns, and the method for making such a die are described. The pitch between the solder bumps is less than 100 microns. A thermal solder jet apparatus is utilized to deposit solder material to form the solder bumps. The apparatus includes a print head having a plurality of solder ejection ports. Each ejection port has an associated gas ejection conduit connected to a chamber containing one or more hydride films for producing hydrogen gas. The hydrogen gas is utilized to force the ejection of the solder material from the ejection port. A controller controls and choreographs the movements of the movable substrate and movable drive so as to accurately deposit material in desired locations on the semiconductor dies.

Abstract: Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which improves device performance and speed.

Abstract: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

Abstract: A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using devices and methods described above. Further, devices and methods provided are able to operate at temperatures much higher than other print head designs such as piezoelectric actuated print heads. Additionally, due to the use of a gas flow restricting device and a recharging gas supply, ejection devices as described above can be used for a substantially extended lifetime, thus making devices and methods described above more economically desirable.

Abstract: Buried conductors within semiconductor devices and structures, and methods for forming such conductors, are disclosed. In one embodiment of the invention, a semiconductor structure includes a substrate and a plurality of conductive elements buried within the substrate. The conductive elements may be metal, such as tungsten or a tungsten alloy.

Abstract: A method of forming micro solder balls for use in a C4 process is described. The solder balls are formed by laying down a peel-away photoresist layer, forming holes in the photoresist layer to expose electrical contacts, depositing a solder layer over the photoresist, forming solder areas in the holes and then, using a tape liftoff process to remove the solder layer and photoresist layer while leaving solder areas in the holes. The solder areas are then heated to allow solder balls to form.