Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.

Abstract: Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive layer to a H2 plasma treatment, and depositing a capping adhesion/barrier layer on the core conductive layer after the H2 plasma treatment. The multilayer dielectric structure provides an insulating layer for around the core conducting layer and at least one sacrificial layer for processing. The H2 plasma treatment removes unwanted oxide from the surface region of the core conducting layer such that the interface between the core conducting layer and the capping adhesion/barrier is substantially free of oxides. In an embodiment, the core conducting layer is copper with a titanium nitride or zirconium capping adhesion/barrier layer.

Abstract: Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for improved coverage of high aspect ratio features with reduced deposition pressure. The alloys are used to fabricate interconnects in integrated circuits, such as memory devices. The interconnects can be high aspect ratio features formed using a dual damascene process. The integrated circuits having the interconnects are applicable to semiconductor dies, devices, modules and systems.

Abstract: A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a semiconductor structure. The system includes a container to hold at least one semiconductor chip having surfaces to be in contact with a fluid. The system also includes a transducer and a heat exchanger disposed within the container and operably positioned with respect to each other to perform a thermoacoustic cooling process. In this system, the transducer is adapted to generate sound waves within the fluid such that compression and decompression of the fluid provides a temperature gradient across the semiconductor chip to transfer heat from the semiconductor chip to the heat exchanger, and the heat exchanger is adapted to remove heat from the fluid in the container. Other aspects and embodiments are provided herein.

Abstract: Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include cleaning using a supercritical fluid. Advantages include a combination of both chemical and mechanical removal abilities from the supercritical fluid. Mechanical energy for cleaning is transmitted in a homogenous manner throughout a carrier fluid. The mechanical energy provided in methods shown also can also be used with delicate surface features.

Abstract: One aspect of this disclosure relates to a method for forming a transistor. According to various method embodiments, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor are formed. A desired gate material is substituted for the substitutable structure to provide the desired gate material on the gate dielectric. Some embodiments use carbon for the substitutable material, and some embodiments use silicon, germanium or silicon-germanium for the substitutable material. Some embodiments form a high-k gate dielectric, such as may be formed by an atomic layer deposition process, an evaporated deposition process, and a metal oxidation process. Other aspects and embodiments are provided herein.

Abstract: A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical floating body transistor with dual gates, one on either side of a vertical pillar of a substrate. One gate is a polysilicon gate and gate insulator that is adjacent to the floating body of the transistor and acts as a DRAM cell. The non-volatile memory cell is constructed on the other side of the pillar with a floating gate or NROM structure. The DRAM and non-volatile cells are linked by a drain region coupling the two cells to a memory array bitline. The bottom of trenches on either side of the pillar have source regions that are linked to respective source lines of the memory array.

Abstract: One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. After the metal layer is formed, voids are formed in the insulator layer. One aspect of the present subject matter relates to an integrated circuit. In various embodiments, the integrated circuit includes an insulator structure having a plurality of voids that have a maximum size, and a metal layer formed in the insulator structure. The maximum size of the voids is larger than the minimum photo dimension of the metal layer such that a maximum-sized void is capable of extending between a first and second metal line in the metal layer. Other aspects are provided herein.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.

Abstract: A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of vaporization temperatures. The plurality of materials is formed on the electronic chip and the conductive structure is coupled to the electronic chip. To fabricate the circuit assembly, a support structure, including interstices, is formed on an electronic chip. The interstices of the support structure are filled with a material having a vaporization temperature that is less than the vaporization temperature of the support structure. Conductive structures are embedded in the support structure and the material, and a connective structure is mounted on the support structure. Finally, the material is removed from the interstices by heating the circuit assembly.

Abstract: A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.

Abstract: A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a semiconductor structure. The system includes a container to hold at least one semiconductor chip having surfaces to be in contact with a fluid. The system also includes a transducer and a heat exchanger disposed within the container and operably positioned with respect to each other to perform a thermoacoustic cooling process. In this system, the transducer is adapted to generate sound waves within the fluid such that compression and decompression of the fluid provides a temperature gradient across the semiconductor chip to transfer heat from the semiconductor chip to the heat exchanger, and the heat exchanger is adapted to remove heat from the fluid in the container. Other aspects and embodiments are provided herein.

Abstract: Devices and methods are described including a conducting pathway with improved electromigration properties. The conducting pathway can be used in integrated circuits and semiconductor chips for devices such as semiconductor memory, or information handling systems. Conducting pathways are provided that eliminate electromigration problems without reducing conductivity in the conductive pathway. Embodiments using a carbon nanotube for the electromigration barrier segment provide the high electrical conductivity of carbon nanotubes, combined with a high resistance to atomic displacement from the nanotube microstructure.

Abstract: A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of various geometries. The empty-spaced patterns are then connected through vias with surfaces of the monocrystalline substrate. The empty-spaced patterns and their respective vias are subsequently filled with conductive materials.

Abstract: One aspect of this disclosure relates to a method for forming a transistor. According to various method embodiments, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor are formed. A desired gate material is substituted for the substitutable structure to provide the desired gate material on the gate dielectric. Some embodiments use carbon for the substitutable material, and some embodiments use silicon, germanium or silicon-germanium for the substitutable material. Some embodiments form a high-k gate dielectric, such as may be formed by an atomic layer deposition process, an evaporated deposition process, and a metal oxidation process. Other aspects and embodiments are provided herein.

Abstract: One aspect of this disclosure relates to a method for forming an integrated circuit. According to various embodiments of the method, a plurality of transistors is formed. For each transistor, a gate dielectric is formed on a substrate, a substitutable structure is formed on the gate dielectric, and source/drain regions for the transistor are formed. At least two substitution processes are performed. Each substitution process includes substituting a desired gate material for the substitutable structure. Other aspects and embodiments are provided herein.

Abstract: One aspect of this disclosure relates to an integrated circuit structure. An integrated circuit structure embodiment includes a substrate, a gate dielectric over the substrate, a carbon structure having a predetermined thickness in contact with and over the gate dielectric, and a layer of desired gate material for a transistor in contact with and over the carbon structure. The layer of desired gate material includes a predetermined thickness corresponding to the predetermined thickness of the carbon structure to support a metal substitution process to replace the carbon structure with the desired gate material. Other aspects and embodiments are provided herein.

Abstract: Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for improved coverage of high aspect ratio features with reduced deposition pressure. The alloys are used to fabricate interconnects in integrated circuits, such as memory devices. The interconnects can be high aspect ratio features formed using a dual damascene process. The integrated circuits having the interconnects are applicable to semiconductor dies, devices, modules and systems.

Abstract: A structure for storing digital data is provided, with a high reflectance layer comprising a noble metal formed over an underlying material layer, and a plurality of low reflectance portions comprising a mixture of a noble metal and an underlying material. The plurality of low reflectance portions have top surfaces comprising a compound of the underlying and the noble metal. A method of changing reflectance on a data storage disk is also disclosed. The method comprises the acts of irradiating a laser light beam onto a noble metal formed over an underlying layer, and raising the temperature of the noble metal above the melting temperature forming a compound of the noble metal and the underlying material.

Abstract: A structure for storing digital data is provided, with a high reflectance layer comprising a gold film formed over a semiconductor layer, and a plurality of low reflectance portions comprising a mixture of a gold material and a semiconductor material. The plurality of low reflectance portions have top surfaces comprising more semiconductor material than the gold material. The invention also provides a method of changing reflectance on a data storage disk, comprising irradiating a laser light beam onto a gold film formed over a semiconductor layer, and raising the temperature of the gold film above a eutectic temperature for a mixture of gold and the semiconductor layer.