Abstract: In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.

Abstract: In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein.

Abstract: A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using devices and methods described above. Further, devices and methods provided are able to operate at temperatures much higher than other print head designs such as piezoelectric actuated print heads. Additionally, due to the use of a gas flow restricting device and a recharging gas supply, ejection devices as described above can be used for a substantially extended lifetime, thus making devices and methods described above more economically desirable.

Abstract: A system for low dielectric constant insulators is provided. One aspect of this disclosure relates to a method for forming an insulator. According to an embodiment of the method, a first structural material is applied as one or more layers of insulation to an integrated circuit surface, a damascene pattern is etched into the first structural material, a first barrier layer and a seed layer are deposited upon the insulation layer, a conductor layer is deposited upon the seed layer, at least a portion of the conductor layer is planarized and at least a portion of the first structural material is removed, a top barrier layer is deposited upon the conductor layer, and a final structural material is applied to replace at least a portion of the first structural material, the final structural material having a lower dielectric constant than the first structural material. Other aspects and embodiments are provided.

Abstract: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

Abstract: Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include cleaning using a supercritical fluid. Advantages include a combination of both chemical and mechanical removal abilities from the supercritical fluid. Mechanical energy for cleaning is transmitted in a homogenous manner throughout a carrier fluid. The mechanical energy provided in methods shown also can also be used with delicate surface features.

Abstract: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.

Abstract: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.

Abstract: An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that the air bridge is suspended above the substrate. The air bridge comprises a highly conductive material, such as silver, so as to provide the air bridge with a reduced resistivity. To inhibit gaseous medium from contaminating the air bridge, the air bridge further comprises an adherent coating interposed between the air bridge and the gaseous medium. A method of forming the electrical interconnect is also disclosed, wherein, prior to forming the adherent coating, the conductive material is processed so as to form fewer grain boundaries, which enhances the electrical properties of the air bridge.

Abstract: A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded in the foamed polymer layer. An insulator is formed by forming a polymer layer having a thickness on a substrate. The polymer layer is foamed to form a foamed polymer layer having a surface and a foamed polymer layer thickness, which is greater than the polymer layer thickness. The surface of the foamed polymer layer is treated to make the surface hydrophobic.

Abstract: Gates of at least one of NMOS transistors and PMOS transistors of a CMOS integrated circuit are formed with a solid-solution alloy of at least two metals. The work function of the gate electrode is tunable by controlling the selection of the metals or the relative proportion of the metals that form a layer of the solid-solution alloy. In one embodiment, a layer of each metal is deposited onto the gate area of a MOS transistor. At least one metal is deposited using atomic layer deposition. The solid-solution alloy is formed by annealing subsequent to the deposition of the metals.

Abstract: Gates of at least one of NMOS transistors and PMOS transistors of a CMOS integrated circuit are formed with an intermetallic compound. The work function of the gate electrode is tunable by controlling the selection of the metals that form a layer of the intermetallic compound. In one embodiment, a layer of each metal is deposited onto the gate area of a MOS transistor. At least one metal is deposited using atomic layer deposition. The intermetallic compound is formed by annealing subsequent to the deposition of the metals.

Abstract: Chemical mechanical polishing (CMP) systems and methods are provided herein. One aspect of the present subject matter is a polishing system. One polishing system embodiment includes a platen adapted to receive a wafer, and a polishing pad drum that has a cylindrical, or generally cylindrical, shape with a length and an axis of rotation along the length. The polishing pad drum is adapted to rotate about the axis of rotation along the drum length. The polishing pad drum, the platen, or both the polishing pad drum and the platen are adapted to be linearly moved to polish the surface of the wafer using the rotating polishing pad drum. The polishing pad drum and the platen are adapted to be operably positioned a predetermined minimum distance from each other as the polishing pad drum and the platen pass each other due the linear motion.

Abstract: Methods of forming solder ball contacts having dimensions of approximately 2.5 microns in diameter for use in C4-type connections. The methods form solder ball contacts using selective deposition of solder on metal contact pads of a device. The metal contact pads have exposed portions at the bottom of through holes. The through holes define the dimensions of the exposed portions of the metal contact pads, and serve to limit the dimensions of the resulting solder contact by limiting the area upon which deposition preferentially occurs. Subsequent reflow of the deposited solder forms a solder ball contact. Various devices, modules, systems and other apparatus utilizing such methods of forming solder ball contacts.

Abstract: Chemical mechanical polishing (CMP) systems and methods are provided herein. One aspect of the present subject matter is a polishing system. One polishing system embodiment includes a platen adapted to receive a wafer, and a polishing pad drum that has a cylindrical, or generally cylindrical, shape with a length and an axis of rotation along the length. The polishing pad drum is adapted to rotate about the axis of rotation along the drum length. The polishing pad drum, the platen, or both the polishing pad drum and the platen are adapted to be linearly moved to polish the surface of the wafer using the rotating polishing pad drum. The polishing pad drum and the platen are adapted to be operably positioned a predetermined minimum distance from each other as the polishing pad drum and the platen pass each other due the linear motion.

Abstract: An improved system and associated methods for the operation and design of integrated circuits at constrained temperature ranges in accordance with bit error rates is disclosed. In one embodiment, a computer is used to derive an operational temperature for the integrated circuit from an assumed bit error rate using the Rice formula. The integrated circuit is then controlled to that temperature by any known temperature-controlling means. Input of the variables to the Rice equation may come from a design module typically used in the design of the integrated circuit, or may be entered by the user based on user preferences. In an alternative embodiment, the system may also be used to design the integrated circuit, again by using the Rice formula.

Abstract: A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for forming an integrated circuit insulator. The method includes forming an insulating layer using a first structural material upon a substrate, the first structural material having sufficient mechanical characteristics to support metal during chemical-mechanical polishing (CMP). The method also includes depositing a metallic layer upon the insulating layer, the metallic layer adapted to be used as a wiring channel. The method further includes processing the metallic layer to form the wiring channel, where processing includes CMP. In addition, the method includes removing and replacing at least a portion of the first structural material with a second structural material, the second structural material having insufficient mechanical characteristics to support metal during CMP. Other aspects and embodiments are provided herein.

Abstract: A semiconductor device structure having a barrier layer comprising a conductive portion and a nonconductive portion is disclosed. The conductive portion includes a metal nitride compound and the nonconductive portion includes a metal oxide, metal oxynitride, metal carbide, or metal carbonitride compound. A method of forming the semiconductor device structure is also disclosed. The method comprises forming a barrier layer over a metallization layer and a dielectric layer in the semiconductor device structure. The barrier layer is formed by depositing a thin, metal layer over the metallization layer and the dielectric layer. The metal layer is exposed to a nitrogen atmosphere and the nitrogen reacts with portions of the metal layer over the metallization layer to form a conductive, metal nitride portion of the barrier layer. Portions of the metal layer over the dielectric layer react with carbon or oxygen in the dielectric layer to produce a nonconductive portion of the barrier layer.