Abstract: A delay circuit, including a connector pad to receive a data input, a pad pin to receive a clock input having a clock edge, a first data line to receive the data input, a second data line to receive the data input, the second data line including a delay circuit that outputs a delayed data output, and at least one logic gate to accept the data input and delayed data output and output a logic state, wherein the logic state determines whether there is a glitch in the delayed data output, and wherein the delay circuit includes at least one delay element to register an output of the at least one logic gate at the clock edge to recognize the glitch.

Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.

Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.

Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.

Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.

Abstract: A method for automation and control of a wireless device in a WiFi environment. The method includes a wireless mobile device configured with a soft access point (softAP) transmitting probe requests to home automation devices and traditional stationary access points. The wireless mobile device periodically wakes up to scan for other services, sends a probe request, authenticates the received probe response from the another device and receives control information via the received probe response.

Abstract: Methods and circuits for measuring the temperature of a transistor are disclosed. An embodiment of the method includes, providing a current into a circuit, wherein the circuit is connected to the transistor. A variable resistance is connected between the base and collector of the transistor. The circuit has a first mode and a second mode, wherein the current in the first mode flows into the base of the transistor and through the resistance and the current in the second mode flows into the emitter of the transistor. Voltages in both the first mode and the second mode are measured using different resistance settings. The temperature of the transistor is calculated based on the difference between the different voltages.

Abstract: A method for automation and control of a wireless device in a WiFi environment. The method includes a wireless mobile device configured with a soft access point (softAP) transmitting probe requests to home automation devices and traditional stationary access points. The wireless mobile device periodically wakes up to scan for other services, sends a probe request, authenticates the received probe response from the another device and receives control information via the received probe response.

Abstract: Methods and circuits for measuring the temperature of a transistor are disclosed. An embodiment of the method includes, providing a current into a circuit, wherein the circuit is connected to the transistor. A variable resistance is connected between the base and collector of the transistor. The circuit has a first mode and a second mode, wherein the current in the first mode flows into the base of the transistor and through the resistance and the current in the second mode flows into the emitter of the transistor. Voltages in both the first mode and the second mode are measured using different resistance settings. The temperature of the transistor is calculated based on the difference between the different voltages.

Abstract: A secure environment is established within a system on a chip (SoC) without the use of a memory management unit. A set of security parameters is produced by a configuration program executed by a processor within the SoC that is read from a first non-volatile memory within the SoC. A set of stored parameters is created in a committable non-volatile memory within the SoC by writing the set of security parameters into the committable non-volatile memory. The committable non-volatile memory is sealed so that that it cannot be read or written by the processor after being sealed. The stored parameters can then be accessed only by control circuitry. Security circuitry within the SoC is configured using the stored parameters each time the SoC is initialized and thereby enforces the secure environment within the SoC.

Abstract: A system comprises an enclosure, host logic contained in the enclosure, and intrusion security logic also contained in the enclosure. The intrusion security logic is coupled to the host logic and configured to detect a security intrusion to the system and to respond to a security intrusion with a user-configurable trigger event. The intrusion security logic implements at least two tamper blocks, each tamper block configured to monitor one more input signals and initiate a trigger event when a security breach of the enclosure is detected. At least one of the tamper blocks comprises a state machine whose operation is controlled by way of user-programmable registers.

Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.

Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.

Abstract: This invention relates to multi-core, multi-processing, factory multi-core and DSP multi-core. The nature of the invention is related to more optimal uses of a multi-core system to maximize utilization of the processor cores and minimize power use. The novel and inventive steps are focused on use of interrupts and prioritized interrupts, along with optional in-built methods, to allow systems to run more efficiently and with less effort on the part of the programmer.

Abstract: A data processing system is provided with a programmable memory protection unit 10 defining a plurality of programmable memory regions 2, 4, 6, 8 each with associated programmable memory attributes. A default memory protection unit 22 is provided and defines a plurality of default memory regions a, b, c, d, e each with associated default memory attributes. If a miss occurs in the programmable memory protection unit 10, and the memory access is a privileged level memory access, then the default memory protection unit 22 will return default memory attributes for that memory request.

Abstract: An integrated gearbox/encoder and control system that includes: a gearbox with an output shaft connected to a mechanical load; a first sensor detecting the rotary position of the output shaft; a motor; a second sensor detecting the rotary position of the motor; and a system controller controlling motive drive to the motor. The two rotary position sensors permit direct determination of gearbox backlash which can be used in motor control. A drive current sensor similarly permits determination of a vibration signature for comparison with a standard.

Abstract: A secure environment is established within a system on a chip (SoC) without the use of a memory management unit. A set of security parameters is produced by a configuration program executed by a processor within the SoC that is read from a first non-volatile memory within the SoC. A set of stored parameters is created in a committable non-volatile memory within the SoC by writing the set of security parameters into the committable non-volatile memory. The committable non-volatile memory is sealed so that that it cannot be read or written by the processor after being sealed. The stored parameters can then be accessed only by control circuitry. Security circuitry within the SoC is configured using the stored parameters each time the SoC is initialized and thereby enforces the secure environment within the SoC.

Abstract: This disclosure describes a processor system that allows non-real time code to execute normally, while permitting a real time interrupt in hardware or software to execute with minimal added latency.

Abstract: An application in a data processing system may automatically select when it needs determinism and when it does not. The ability to have the system automatically select when to use each allows optimum system performance while maintaining hard real-time requirements when needed.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.