Abstract: Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.

Abstract: Apparatus and methods for wirelessly communicating using antennas are disclosed. In certain embodiments, an antenna system includes a first radio frequency signal conditioning circuit configured to condition a first radio frequency signal of a first frequency, a plurality of second radio frequency signal conditioning circuits configured to condition a plurality of second radio frequency signals of a second frequency that is greater than the first frequency, a plurality of switches operable in a first mode and a second mode, and an antenna array of including a plurality of antenna elements interconnect by the plurality of switches. The antenna array is operable to handle the first radio frequency signal in the first mode, and to handle the plurality of second radio frequency signals in the second mode.

Abstract: Disclosed herein are silicon-on-insulator (SOI) switches and associated control circuits having level shifters configured to provide increased voltages (positive and/or negative) to the switches. The disclosed level shifters can be configured to provide increased voltages and can be used with high-linearity switches and/or can improve the linearity of switches. The improved switch performance can improve front end module performance for applications such as carrier aggregation (CA) and multiple input multiple output (MIMO) as well as with protocols such as Long-Term Evolution Advanced (or LTE-A).

Abstract: Apparatus and methods for envelope controlled radio frequency (RF) switches are provided. In certain embodiments, a power amplifier provides an RF signal to an antenna by way of an RF switch. Additionally, the envelope signal is used not only to control a power amplifier supply voltage of the power amplifier, but also to control a regulated voltage used to turn on the RF switch. For example, a level shifter can use a regulated voltage from charge pump circuitry to turn on the RF switch, and the envelope signal can be provided to the charge pump circuitry and used to control the voltage level of the regulated voltage over time.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Described herein are switches with asymmetrical anti-series varactor pairs to improve switching performance. The disclosed switches can include asymmetrical varactor pairs to reduce distortions. The asymmetry in the varactor pairs can be associated with geometry of each varactor in the pair. The disclosed switches can stack both symmetrical and asymmetrical varactor pairs. The disclosed switches with asymmetrical anti-series varactor pairs can be configured to improve both H2 and H3 simultaneously.

Abstract: Apparatus and methods for multi-antenna communications are provided. In certain embodiments, a communication system includes an antenna array including a plurality of antenna elements, and a plurality of RF circuit channels each coupled to a corresponding one of the antenna elements. The plurality of RF circuit channels generate two or more analog baseband signals in response to the antenna array receiving a radio wave. The communication system further includes a controllable amplification and combining circuit that generates two or more amplified analog baseband signals based on amplifying each of the two or more analog baseband signals with a separately controllable gain, and that combines the two or more amplified analog baseband signals to generate a combined analog baseband signal.

Abstract: Disclosed herein are non-limiting examples of voltage generators that use multiple charge pumps coupled in series to generate a targeted voltage. The charge pumps implement multiple charge pump units that reduce the introduction of noise into a circuit in which they are implemented. The charge pumps units work in parallel on different clock phases to reduce spurious noise. This is in contrast to using a single charge pump with a relatively large flying capacitor or a plurality of charge pumps in series. This can, for example, reduce spurious signals or spurs that arise due at least in part to the characteristics of the clock signal. The disclosed technologies may be particularly advantageous for SOI-based components and circuits.

Abstract: Apparatus and methods for multi-antenna communications are provided. In certain embodiments, a communication system includes an antenna array including a plurality of antenna elements, and a plurality of RF circuit channels each coupled to a corresponding one of the antenna elements. The plurality of RF circuit channels generate two or more analog baseband signals in response to the antenna array receiving a radio wave. The communication system further includes a controllable amplification and combining circuit that generates two or more amplified analog baseband signals based on amplifying each of the two or more analog baseband signals with a separately controllable gain, and that combines the two or more amplified analog baseband signals to generate a combined analog baseband signal.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Apparatus and methods for envelope alignment calibration in radio frequency (RF) systems are provided. In certain embodiments, calibration is performed by providing an envelope signal that is substantially triangular along an envelope path, and by providing an RF signal to a power amplifier along an RF signal path. Additionally, an output of the power amplifier is observed to generate an observation signal using an observation receiver. The observation signal includes a first peak and a second peak, and a delay between the envelope signal and the RF signal is controlled based on relative size of the peaks of the observation signal to one another.

Abstract: Disclosed herein are non-limiting examples of charge pumps that reduce the introduction of noise into a circuit in which they are implemented and/or lower the output impedance when providing certain voltages (e.g., negative voltage generators). The disclosed technologies utilize a plurality of smaller charge pumps (or charge pump units) working in parallel that operate on different clock phases rather than using a single charge pump with a relatively large flying capacitor or a plurality of charge pumps in series. This can, for example, reduce spurious signals or spurs that arise due at least in part to the characteristics of the clock signal. The disclosed technologies may be particularly advantageous for SOI-based components and circuits.

Abstract: Apparatus and methods for envelope alignment calibration in radio frequency (RF) systems are provided. In certain embodiments, calibration is performed by providing an envelope signal with a peak along an envelope path, and by providing an RF signal with a first peak and a second peak to a power amplifier along an RF signal path. Additionally, an output of the power amplifier is observed to generate an observation signal using an observation receiver. The observation signal includes a first peak and a second peak corresponding to the first peak and the second peak of the RF signal, and a delay between the envelope signal and the RF signal is controlled based on relative size of the peaks of the observation signal to one another.

Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.

Abstract: A method of fabricating a cascode amplifier including a common-source device and a common-gate device includes performing one or more of ion implantation of a well of the common-source device, ion implantation of a source extension and/or drain extension of the common-source device, or a halo ion implantation of the common-source device with one or more of a different ionic species, a different dosage, a different energy, or a different tilt angle than a corresponding one or more of ion implantation of a well of the common-gate device, ion implantation of a source and/or drain extension of the common-gate device, or a halo ion implantation of the common-gate device.

Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly.

Abstract: Apparatus and methods for multi-antenna communications are provided. In certain embodiments, a communication system includes an antenna array including a plurality of antenna elements, and a plurality of RF circuit channels each coupled to a corresponding one of the antenna elements. The plurality of RF circuit channels generate two or more analog baseband signals in response to the antenna array receiving a radio wave. The communication system further includes a controllable amplification and combining circuit that generates two or more amplified analog baseband signals based on amplifying each of the two or more analog baseband signals with a separately controllable gain, and that combines the two or more amplified analog baseband signals to generate a combined analog baseband signal.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.