Abstract: Disclosed herein are silicon-on-insulator (SOI) switches and associated control circuits having level shifters configured to provide increased voltages (positive and/or negative) to the switches. The disclosed level shifters can be configured to provide increased voltages and can be used with high-linearity switches and/or can improve the linearity of switches. The improved switch performance can improve front end module performance for applications such as carrier aggregation (CA) and multiple input multiple output (MIMO) as well as with protocols such as Long-Term Evolution Advanced (or LTE-A).

Abstract: Apparatus and methods for envelope alignment calibration in radio frequency (RF) systems are provided. In certain embodiments, calibration is performed by providing an envelope signal with a peak along an envelope path, and by providing an RF signal with a first peak and a second peak to a power amplifier along an RF signal path. Additionally, an output of the power amplifier is observed to generate an observation signal using an observation receiver. The observation signal includes a first peak and a second peak corresponding to the first peak and the second peak of the RF signal, and a delay between the envelope signal and the RF signal is controlled based on relative size of the peaks of the observation signal to one another.

Abstract: Apparatus and methods for envelope controlled radio frequency (RF) switches are provided. In certain embodiments, a power amplifier provides an RF signal to an antenna by way of an RF switch. Additionally, the envelope signal is used not only to control a power amplifier supply voltage of the power amplifier, but also to control a regulated voltage used to turn on the RF switch. For example, a level shifter can use a regulated voltage from charge pump circuitry to turn on the RF switch, and the envelope signal can be provided to the charge pump circuitry and used to control the voltage level of the regulated voltage over time.

Abstract: A cascode amplifier including a common-source device and a common-gate device formed utilizing different processing parameters to separately optimize performance of the common-source device and common-gate device.

Abstract: Discharge circuits, devices and methods. In some embodiments, a MEMS device can include a substrate and an electromechanical assembly implemented on the substrate. The MEMS device can further include a discharge circuit implemented relative to the electromechanical assembly. The discharge circuit can be configured to provide a preferred arcing path during a discharge condition affecting the electromechanical assembly. The MEMS device can be, for example, a switching device, a capacitance device, a gyroscope sensor device, an accelerometer device, a surface acoustic wave (SAW) device, or a bulk acoustic wave (BAW) device. The discharge circuit can include a spark gap assembly having one or more spark gap elements configured to facilitate the preferred arcing path.

Abstract: Circuits, systems, and methods to compensate for non-linearities associated with a switching circuit are discussed herein. For example, a switch circuit can include a switch arm and a linearizer arm. The switch arm can have a first transistor connected between an input node and an output node. The switch arm can be configured to receive a radio-frequency signal. The linearizer arm can have a second transistor connected to at least one of a gate or a body of the first transistor. The linearizer arm can be configured to compensate a non-linearity effect generated by the switch arm.

Abstract: Disclosed herein are switching or other active field-effect transistor (FET) configurations that implement independently controlled main-auxiliary branch designs. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FET devices in parallel with a plurality of auxiliary FET devices. The circuit assembly can include a plurality of gate bias networks where each controls one or more of the main FET devices. The circuit assembly includes a second plurality of gate bias networks that each controls one or more of the auxiliary FET devices.

Abstract: Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.

Abstract: Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device.

Abstract: Apparatus and methods for multi-antenna communications are provided. In certain embodiments, a communication system includes an antenna array including a plurality of antenna elements, and a plurality of RF circuit channels each coupled to a corresponding one of the antenna elements. The plurality of RF circuit channels generate two or more analog baseband signals in response to the antenna array receiving a radio wave. The communication system further includes a controllable amplification and combining circuit that generates two or more amplified analog baseband signals based on amplifying each of the two or more analog baseband signals with a separately controllable gain, and that combines the two or more amplified analog baseband signals to generate a combined analog baseband signal.

Abstract: Envelope tracking can be employed to reduce power consumption of a power amplifier, but envelope tracking can introduce nonlinearities to a power amplifier. These nonlinearities can manifest themselves as noise at the output of the power amplifier. Embodiments described herein provide techniques for characterizing a parameter indicative of power amplifier noise when envelope tracking is employed. Measurement of this parameter can permit power amplifier designers to decide whether to forgo envelope tracking if a power amplifier is too susceptible to such noise, redesign the power amplifier to improve compatibility with envelope tracking, or to employ distortion compensation circuitry to reduce the noise output by the power amplifier. Counterintuitively, this distortion compensation circuitry may involve increasing the power, such as the envelope tracking power supply. However, increasing the power may be a desirable trade-off for increased linearity.

Abstract: Disclosed herein are circuits, devices and methods that address challenges associated with power amplifier systems. A power amplifier system includes two or more fast error amplifiers coupled to corresponding power amplifiers. The fast error amplifiers are configured to generate envelope tracking signals based on a signal envelope, the envelope tracking signals modifying a DC-DC regulated voltage from a DC-DC converter to more efficiently operate the power amplifiers. By splitting the envelope tracking between two or more fast error amplifiers and amplification between corresponding two or more power amplifiers, the power, frequency or bandwidth, linearity, signal-to-noise ratio, efficiency, or the like of the power amplifier system can be improved. Wireless communications configurations with such power amplifier systems can provide uplink carrier aggregation and/or cellular signals based on standards and protocols that require increased bandwidth and/or power.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Disclosed herein are silicon-on-insulator (SOI) switches and associated control circuits having level shifters configured to provide increased voltages (positive and/or negative) to the switches. The disclosed level shifters can be configured to provide increased voltages and can be used with high-linearity switches and/or can improve the linearity of switches. The improved switch performance can improve front end module performance for applications such as carrier aggregation (CA) and multiple input multiple output (MIMO) as well as with protocols such as Long-Term Evolution Advanced (or LTE-A).

Abstract: Disclosed herein are circuits, devices and methods that address challenges associated with power amplifier systems. A power amplifier system includes two or more fast error amplifiers coupled to corresponding power amplifiers. The fast error amplifiers are configured to generate envelope tracking signals based on a signal envelope, the envelope tracking signals modifying a DC-DC regulated voltage from a DC-DC converter to more efficiently operate the power amplifiers. By splitting the envelope tracking between two or more fast error amplifiers and amplification between corresponding two or more power amplifiers, the power, frequency or bandwidth, linearity, signal-to-noise ratio, efficiency, or the like of the power amplifier system can be improved. Wireless communications configurations with such power amplifier systems can provide uplink carrier aggregation and/or cellular signals based on standards and protocols that require increased bandwidth and/or power.

Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

Abstract: Disclosed herein are switching or other active field-effect transistor (FET) configurations that implement independently controlled main-auxiliary branch designs. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FET devices in parallel with a plurality of auxiliary FET devices. The circuit assembly can include a plurality of gate bias networks where each controls one or more of the main FET devices. The circuit assembly includes a second plurality of gate bias networks that each controls one or more of the auxiliary FET devices.

Abstract: Disclosed herein are amplification systems that are dynamically biased based on a signal indicative of an envelope of an input radio-frequency (RF) signal being amplified. The amplification systems include a power converter with an envelope tracker and an RC circuit. The envelope tracker and the RC circuit are configured to generate an envelope-based biasing signal to bias a power amplifier and an envelope-based supply voltage to power the power amplifier.

Abstract: Disclosed herein are switching or other active FET configurations that implement a segmented main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a plurality of main-auxiliary pairs coupled in series, wherein each main-auxiliary pair includes a main field-effect transistor (FET) in parallel with an auxiliary FET. The circuit assembly also includes a gate bias network connected to the main FETs and configured to bias the main FETs in a strong inversion region. The circuit assembly also includes an auxiliary bias network connected to the auxiliary FETs and configured to bias the auxiliary FETs in a weak inversion region.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with a first auxiliary path and the main path in series with a second auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the first auxiliary path. The circuit assembly also includes a third gate bias network connected to the second auxiliary path, the second gate bias network and the third gate bias network configured to improve linearity of the switching function.