Patents by Inventor Pei-Ren Jeng

Pei-Ren Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190136378
    Abstract: A semiconductor fabrication apparatus includes a processing chamber; a wafer stage configured in the processing chamber; a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber; and air edge mechanisms configured on both sides of the first reaction zone to isolate the first reaction zone from other reaction zones in the processing chamber.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 10161039
    Abstract: A semiconductor fabrication apparatus includes a processing chamber, a wafer stage configured in the processing chamber, a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber, and a second chemical delivery mechanism configured in the processing chamber to provide a second chemical to a second reaction zone in the processing chamber. The second chemical delivery mechanism includes an edge chemical injector and a first radial chemical injector both configured to deliver the second chemical to the second reaction zone.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Publication number: 20180350906
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Patent number: 10084040
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20180142351
    Abstract: A semiconductor fabrication apparatus includes a processing chamber, a wafer stage configured in the processing chamber, a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber, and a second chemical delivery mechanism configured in the processing chamber to provide a second chemical to a second reaction zone in the processing chamber. The second chemical delivery mechanism includes an edge chemical injector and a first radial chemical injector both configured to deliver the second chemical to the second reaction zone.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 24, 2018
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Publication number: 20180090608
    Abstract: A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 29, 2018
    Inventors: Ming-Hua Yu, Chih-Pin Tsao, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 9911829
    Abstract: A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 9873943
    Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a processing chamber; a wafer stage configured in the processing chamber, the wafer stage is operable to secure and rotate a plurality of wafers around an axis; a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber; and a second chemical delivery mechanism configured in the processing chamber to provide a second chemical to a second reaction zone in the processing chamber. The second chemical delivery mechanism includes an edge chemical injector and a first radial chemical injector.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Publication number: 20180019133
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, and a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The integrated circuit further includes a seal formed on sidewalls of the metal gate structure. The integrated circuit further includes a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure.
    Type: Application
    Filed: September 27, 2017
    Publication date: January 18, 2018
    Inventors: Jin-Aun Ng, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu
  • Patent number: 9865709
    Abstract: A method of fabricating a fin field-effect transistor (FinFET) device is provided. The method includes forming a carbon-based layer on a plurality of gate structures formed on a semiconductor substrate. Each gate structure overlies at least one fin formed on the semiconductor substrate. The carbon-based layer covers sidewalls of the gate structures. A metal silicide layer overlies the carbon-based layer. The metal silicide layer and carbon-based layer are removed, and a metal layer is formed between adjacent gate structures.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsai-Jung Ho, Pei-Ren Jeng
  • Patent number: 9859386
    Abstract: An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Jung Ho, Kuang-Yuan Hsu, Pei-Ren Jeng
  • Patent number: 9831345
    Abstract: A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Chih-Pin Tsao, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 9818846
    Abstract: A method of fabricating a fin field-effect transistor (FinFET) device is provided. The method includes forming a carbon-based layer on a plurality of gate structures formed on a semiconductor substrate. Each gate structure overlies at least one fin formed on the semiconductor substrate. The carbon-based layer covers sidewalls of the gate structures. A metal silicide layer overlies the carbon-based layer. The metal silicide layer and carbon-based layer are removed, and a metal layer is formed between adjacent gate structures.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsai-Jung Ho, Pei-Ren Jeng
  • Publication number: 20170317192
    Abstract: A method of fabricating a fin field-effect transistor (FinFET) device is provided. The method includes forming a carbon-based layer on a plurality of gate structures formed on a semiconductor substrate. Each gate structure overlies at least one fin formed on the semiconductor substrate. The carbon-based layer covers sidewalls of the gate structures. A metal silicide layer overlies the carbon-based layer. The metal silicide layer and carbon-based layer are removed, and a metal layer is formed between adjacent gate structures.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Tsai-Jung HO, Pei-Ren JENG
  • Publication number: 20170288031
    Abstract: An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.
    Type: Application
    Filed: January 16, 2017
    Publication date: October 5, 2017
    Inventors: Tsai-Jung Ho, Kuang-Yuan Hsu, Pei-Ren Jeng
  • Patent number: 9779980
    Abstract: A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ling Liou, Chih-Tang Peng, Pei-Ren Jeng, Hao-Ming Lien, Tze-Liang Lee
  • Patent number: 9779947
    Abstract: An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jin-Aun Ng, Jen-Sheng Yang, Pei-Ren Jeng, Jung-Hui Kao, Shih-Hao Lo, Yuan-Tien Tu, Bao-Ru Young, Harry-Hak-Lay Chuang, Maxi Chang, Chih-Tang Peng, Chih-Yang Yeh, Ta-Wei Lin, Huan-Just Lin, Hui-Wen Lin
  • Patent number: 9768044
    Abstract: A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Wang, Yu-Chang Lin, Li-Ting Wang, Tai-Chun Huang, Pei-Ren Jeng, Tze-Liang Lee
  • Publication number: 20170213901
    Abstract: A method of fabricating a fin field-effect transistor (FinFET) device is provided. The method includes forming a carbon-based layer on a plurality of gate structures formed on a semiconductor substrate. Each gate structure overlies at least one fin formed on the semiconductor substrate. The carbon-based layer covers sidewalls of the gate structures. A metal silicide layer overlies the carbon-based layer. The metal silicide layer and carbon-based layer are removed, and a metal layer is formed between adjacent gate structures.
    Type: Application
    Filed: September 8, 2016
    Publication date: July 27, 2017
    Inventors: Tsai-Jung HO, Pei-Ren JENG
  • Publication number: 20170194424
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Application
    Filed: October 11, 2016
    Publication date: July 6, 2017
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee