Patents by Inventor Pei-Yu Chou

Pei-Yu Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10921876
    Abstract: Power and performance of a multi-core system is managed dynamically by adjusting power table indices at runtime. Runtime statistics is measured, when an application is executed on a first core of a first type at a first operating point (OPP) in a first time period, and on a second core of a second core type at a second OPP in a second time period. A controller estimates, based on the runtime statistics, a first pair of indices associated with a first OPP for the first core and a second pair of indices associated with a second OPP for the second core. During runtime, the controller incorporates the first pair of indices and the second pair of indices into power table indices; and determines, from the power table indices, selected indices associated with a selected OPP of a core of a selected core type for executing the application.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: February 16, 2021
    Assignee: MediaTek Inc.
    Inventors: Jih-Ming Hsu, Tai-Hua Lu, Pei-Yu Huang, Chien-Yuan Lai, Shu-Hsuan Chou, I-Cheng Cheng, Yun-Ching Li, Ming Hsien Lee
  • Publication number: 20200388692
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Chun-Hsiung LIN, Chia-Hao CHANG, Chih-Hao WANG, Wai-Yi LIEN, Chih-Chao CHOU, Pei-Yu WANG
  • Patent number: 10834127
    Abstract: An email attempting to perpetrate a business email compromise (BEC) attack is detected based on similarity of the email to a known BEC email and on similarity of the email to a user email that would have been sent by the purported sender of the email. Metadata of the email is extracted and input to a BEC machine learning model to find the known BEC email among BEC email samples. The extracted metadata are also input to a personal user machine learning model of the purported sender to generate the user email.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 10, 2020
    Assignee: Trend Micro Incorporated
    Inventors: Che-Fu Yeh, I-Ting Lien, Ming-Lun Li, Shih-Yu Chou, Po-Yuan Teng, Yuan Jiun Tsui, Cheng-Hsin Hsu, Wen-Kwang Tsao, Shih-Han Hsu, Pei-Yin Wu, Jonathan James Oliver
  • Publication number: 20200350416
    Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
    Type: Application
    Filed: July 13, 2020
    Publication date: November 5, 2020
    Inventors: Chia-Ming HSU, Pei-Yu CHOU, Chih-Pin TSAO, Kuang-Yuan HSU, Jyh-Huei CHEN
  • Patent number: 10763328
    Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. A first epitaxial layer has a first surface and a second surface inclined relative to the first surface. A surface layer is arranged on the first and second surfaces of the first epitaxial layer. A second epitaxial layer is arranged over the surface layer on the first and second surfaces of the first epitaxial layer. A portion of the first epitaxial layer defines an interface with the surface layer. The portion of the first epitaxial layer contains a first concentration of a dopant. The surface layer contains a second concentration of the dopant that is greater than the first concentration of the dopant in the portion of the first epitaxial layer.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: September 1, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Omur Isil Aydin, Judson Holt, Lakshmanan Vanamurthy, Tobias Heyne, Pei-Yu Chou, Cäcilia Brantz
  • Patent number: 10756197
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Patent number: 10756196
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Patent number: 10714586
    Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Hsu, Pei-Yu Chou, Chih-Pin Tsao, Kuang-Yuan Hsu, Jyh-Huei Chen
  • Publication number: 20200111870
    Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. A first epitaxial layer has a first surface and a second surface inclined relative to the first surface. A surface layer is arranged on the first and second surfaces of the first epitaxial layer. A second epitaxial layer is arranged over the surface layer on the first and second surfaces of the first epitaxial layer. A portion of the first epitaxial layer defines an interface with the surface layer. The portion of the first epitaxial layer contains a first concentration of a dopant. The surface layer contains a second concentration of the dopant that is greater than the first concentration of the dopant in the portion of the first epitaxial layer.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 9, 2020
    Inventors: Omur Isil Aydin, Judson Holt, Lakshmanan Vanamurthy, Tobias Heyne, Pei-Yu Chou, Cäcilia Brantz
  • Publication number: 20200035805
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung LIN, Chia-Hao CHANG, Chih-Hao WANG, Wai-Yi LIEN, Chih-Chao CHOU, Pei-Yu WANG
  • Publication number: 20200027960
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Chun-Hsiung LIN, Chia-Hao CHANG, Chih-Hao WANG, Wai-Yi LIEN, Chih-Chao CHOU, Pei-Yu WANG
  • Patent number: 10510860
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Publication number: 20190332157
    Abstract: Power and performance of a multi-core system is managed dynamically by adjusting power table indices at runtime. Runtime statistics is measured, when an application is executed on a first core of a first type at a first operating point (OPP) in a first time period, and on a second core of a second core type at a second OPP in a second time period. A controller estimates, based on the runtime statistics, a first pair of indices associated with a first OPP for the first core and a second pair of indices associated with a second OPP for the second core. During runtime, the controller incorporates the first pair of indices and the second pair of indices into power table indices; and determines, from the power table indices, selected indices associated with a selected OPP of a core of a selected core type for executing the application.
    Type: Application
    Filed: April 26, 2018
    Publication date: October 31, 2019
    Inventors: Jih-Ming Hsu, Tai-Hua Lu, Pei-Yu Huang, Chien-Yuan Lai, Shu-Hsuan Chou, I-Cheng Cheng, Yun-Ching Li, Ming Hsien Lee
  • Patent number: 10153351
    Abstract: In a method of manufacturing a semiconductor device, a first contact hole is formed in one or more dielectric layers disposed over a source/drain region or a gate electrode. An adhesive layer is formed in the first contact hole. A first metal layer is formed on the adhesive layer in the first contact hole. A silicide layer is formed on an upper surface of the first metal layer. The silicide layer includes a same metal element as the first metal layer.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Hsu, Chih-Pin Tsao, Jyh-Huei Chen, Kuang-Yuan Hsu, Pei-Yu Chou
  • Publication number: 20180337244
    Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Chia-Ming HSU, Pei-Yu CHOU, Chih-Pin TSAO, Kuang-Yuan HSU, Jyh-Huei CHEN
  • Patent number: 9741625
    Abstract: In a first aspect, the present disclosure provides a method of forming a semiconductor device, including providing an SOI structure comprising a base substrate, a buried insulating material layer formed on the base substrate and an active semiconductor layer formed on the buried insulating structure, forming a germanium-comprising layer on an exposed surface of the active semiconductor layer, forming a trench isolation structure, the trench isolation structure extending through the germanium-comprising layer and the active semiconductor layer, performing an annealing process after the trench isolation structure is formed, the annealing process resulting in an oxide layer disposed on a germanium-comprising active layer which is formed on the buried insulating material layer, and removing the oxide layer for exposing an upper surface of the germanium-comprising active layer.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ran Yan, Alban Zaka, Pei-Yu Chou
  • Publication number: 20170222008
    Abstract: In a method of manufacturing a semiconductor device, a first contact hole is formed in one or more dielectric layers disposed over a source/drain region or a gate electrode. An adhesive layer is formed in the first contact hole. A first metal layer is formed on the adhesive layer in the first contact hole. A silicide layer is formed on an upper surface of the first metal layer. The silicide layer includes a same metal element as the first metal layer.
    Type: Application
    Filed: December 14, 2016
    Publication date: August 3, 2017
    Inventors: Chia-Ming HSU, Chih-Pin TSAO, Jyh-Huei CHEN, Kuang-Yuan HSU, Pei-Yu CHOU
  • Publication number: 20170069550
    Abstract: In a first aspect, the present disclosure provides a method of forming a semiconductor device, including providing an SOI structure comprising a base substrate, a buried insulating material layer formed on the base substrate and an active semiconductor layer formed on the buried insulating structure, forming a germanium-comprising layer on an exposed surface of the active semiconductor layer, forming a trench isolation structure, the trench isolation structure extending through the germanium-comprising layer and the active semiconductor layer, performing an annealing process after the trench isolation structure is formed, the annealing process resulting in an oxide layer disposed on a germanium-comprising active layer which is formed on the buried insulating material layer, and removing the oxide layer for exposing an upper surface of the germanium-comprising active layer.
    Type: Application
    Filed: September 3, 2015
    Publication date: March 9, 2017
    Inventors: Ran Yan, Alban Zaka, Pei-Yu Chou
  • Patent number: 9502530
    Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.
    Type: Grant
    Filed: November 8, 2015
    Date of Patent: November 22, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
  • Publication number: 20160064521
    Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.
    Type: Application
    Filed: November 8, 2015
    Publication date: March 3, 2016
    Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng