Abstract: A method of descumming a patterned photoresist is provided. First a material layer to be etched is provided. The material layer is covered by a patterned photoresist. Then a descum process is preformed to descum the edge of the patterned photoresist by nitrogen. Finally, the descummed patterned photoresist is used as a mask for etching the material layer.

Abstract: First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

Abstract: A strained-silicon CMOS transistor includes: a semiconductor substrate having a first active region, a second active region, and an isolation structure disposed between the first active region and the second active region; a first transistor, disposed on the first active region; a second transistor, disposed on the second active region; a first etching stop layer, disposed on the first transistor and the second transistor; a first stress layer, disposed on the first transistor; a second etching stop layer, disposed on the first transistor and the first stress layer, wherein an edge of the first stress layer is aligned with that of the second etching stop layer; a second stress layer, disposed on the second transistor; and a third etching stop layer disposed on the second transistor and the second stress layer, wherein an edge of the second stress layer is aligned with that of the third etching stop layer.

Abstract: An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings.

Abstract: First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

Abstract: A method for fabricating an aperture is disclosed. The method includes the steps of: depositing a dielectric layer and a hard mask on surface of a semiconductor substrate; patterning the hard mask by forming an aperture in the hard mask; utilizing a gas containing CaXb and CdHXe to perform a pre-treatment on the patterned hard mask and the dielectric layer, in which a, b, d and e from CaXb and CdHXe are integers and X represents halogen atom; and performing an etching process to transfer the aperture into the dielectric layer.

Abstract: The method of manufacturing an imprinting template according to the present invention utilizes a semiconductor manufacturing process and comprises a step of etching an oxide layer having a thickness of from 1000 to 8000 angstroms on a substrate by a microlithography and etching process, to form a pattern having a plurality of pillar-shaped holes, thereby forming an imprinting plate having a plurality of pillar-shaped holes. A material layer may be filled into the holes and a part of the oxide layer is removed to form an imprinting template having a plurality of pillar-shaped protrusions. Alternatively, a silicon substrate may be used instead of the substrate and the oxide layer. The imprinting template according to the present invention has advantages of mass production, fast production, and low cost, and is suitable to serve as the imprinting plate for making photonic crystals.

Abstract: A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance.

Abstract: A method of forming openings is disclosed. A substrate is first provided, and the tri-layer structure is formed on the substrate. The tri-layer structure includes a bottom photoresist layer, a silicon-containing layer and a top photoresist layer form bottom to top. Subsequently, the top photoresist layer is patterned, and the silicon-containing layer is etched by utilizing the top photoresist layer as an etching mask to partially expose the bottom photoresist layer. Next, the partially exposed bottom photoresist layer is etched through two etching steps in turn by utilizing the patterned silicon-containing layer as an etching mask. The first etching step includes an oxygen gas and at least one non-carbon-containing halogen-containing gas, while the second etching step includes at least one halogen-containing gas. The substrate is thereafter etched by utilizing the patterned bottom photoresist layer as an etching mask to form at least an opening in the substrate.

Abstract: A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance.

Abstract: A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation structure. Further, the first-type MOS transistor is disposed on the first active area of the substrate, and the second-type MOS transistor is disposed on the second active area of the substrate. The first stress layer is compliantly disposed on the first-type MOS transistor of the first active area. The first liner layer is compliantly disposed on the first stress layer. The second stress layer is compliantly disposed on the second-type MOS transistor of the second active area.

Abstract: A method of forming openings is disclosed. A substrate is first provided, and the tri-layer structure is formed on the substrate. The tri-layer structure includes a bottom photoresist layer, a silicon-containing layer and a top photoresist layer form bottom to top. Subsequently, the top photoresist layer is patterned, and the silicon-containing layer is etched by utilizing the top photoresist layer as an etching mask to partially expose the bottom photoresist layer. Next, the partially exposed bottom photoresist layer is etched through two etching steps in turn by utilizing the patterned silicon-containing layer as an etching mask. The first etching step includes an oxygen gas and at least one non-carbon-containing halogen-containing gas, while the second etching step includes at least one halogen-containing gas. The substrate is thereafter etched by utilizing the patterned bottom photoresist layer as an etching mask to form at least an opening in the substrate.

Abstract: A method of forming a metal-oxide-semiconductor (MOS) device is provided. The method includes the following steps. First, a conductive type MOS transistor is formed on a substrate. Then, a first etching stop layer is formed over the substrate to cover conformably the conductive type MOS transistor. Thereafter, a stress layer is formed over the first etching stop layer. Then, a second etching stop layer is formed over the stress layer.

Abstract: A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.

Abstract: A method for fabricating a contact hole is provided. A semiconductor substrate having thereon a conductive region is prepared. A dielectric layer is deposited on the semiconductor substrate and the conductive region. An etching resistive layer is coated on the dielectric layer. A silicon-containing hard mask bottom anti-reflection coating (SHB) layer is then coated on the etching resistive layer. A photoresist layer is then coated on the SHB layer. A lithographic process is performed to form a first opening in the photoresist layer. Using the photoresist layer as a hard mask, the SHB layer is etched through the first opening, thereby forming a shrunk, tapered second opening in the SHB layer. Using the etching resistive layer as an etching hard mask, etching the dielectric layer through the second opening to form a contact hole in the dielectric layer.

Abstract: A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios.

Abstract: A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Abstract: A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

Abstract: A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

Abstract: A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance.