Patents by Inventor Pei-Yu Chou
Pei-Yu Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160064521Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.Type: ApplicationFiled: November 8, 2015Publication date: March 3, 2016Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
-
Patent number: 9214395Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.Type: GrantFiled: March 13, 2013Date of Patent: December 15, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
-
Publication number: 20140273368Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
-
Patent number: 8829575Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.Type: GrantFiled: December 26, 2012Date of Patent: September 9, 2014Assignee: United Microelectronics Corp.Inventors: Chung-Fu Chang, Yu-Hsiang Hung, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
-
Patent number: 8828815Abstract: First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.Type: GrantFiled: December 3, 2010Date of Patent: September 9, 2014Assignee: United Microelectronics Corp.Inventors: Pei-Yu Chou, Shih-Fang Tzou, Jiunn-Hsiung Liao
-
Patent number: 8772120Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers.Type: GrantFiled: May 24, 2012Date of Patent: July 8, 2014Assignee: United Microelectronics Corp.Inventors: Chung-Fu Chang, Yu-Hsiang Hung, Shin-Chuan Huang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou
-
Publication number: 20140175527Abstract: A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu Chang, Yu-Hsiang Hung, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
-
Patent number: 8753902Abstract: A method of controlling an etching process for forming an epitaxial structure includes the following steps. A substrate having a gate thereon is provided. A spacer is formed on the substrate beside the gate to define the position of the epitaxial structure. A thickness of the spacer is measured. The etching time of a first etching process is set according to the thickness. The first etching process is performed to form a recess in the substrate beside the spacer. The epitaxial structure is formed in the recess.Type: GrantFiled: March 13, 2013Date of Patent: June 17, 2014Assignee: United Microelectronics Corp.Inventors: Chia-Jong Liu, Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Pei-Yu Chou, Home-Been Cheng
-
Patent number: 8673544Abstract: A method for forming openings is provided. First, a substrate with a silicon-containing photo resist layer thereon is provided. Second, a first photo resist pattern is formed on the silicon-containing photo resist layer. Later, a first etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of first openings by using the first photo resist pattern as an etching mask. Next, a second photo resist pattern is formed on the silicon-containing photo resist layer. Then, a second etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of second openings by using the second photo resist pattern as an etching mask.Type: GrantFiled: March 27, 2012Date of Patent: March 18, 2014Assignee: United Microelectronics Corp.Inventors: Pei-Yu Chou, Jiunn-Hsiung Liao
-
Publication number: 20130316506Abstract: A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers.Type: ApplicationFiled: May 24, 2012Publication date: November 28, 2013Inventors: Chung-Fu Chang, Yu-Hsiang Hung, Shin-Chuan Huang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou
-
Patent number: 8592322Abstract: A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.Type: GrantFiled: June 28, 2012Date of Patent: November 26, 2013Assignee: United Microelectronics Corp.Inventors: Feng-Yi Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin, Po-Chao Tsao
-
Patent number: 8574990Abstract: The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.Type: GrantFiled: February 24, 2011Date of Patent: November 5, 2013Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Shui-Yen Lu, Pei-Yu Chou, Shin-Chi Chen, Jiunn-Hsiung Liao, Shang-Yuan Tsai, Chan-Lon Yang, Teng-Chun Tsai, Chun-Hsien Lin
-
Patent number: 8461649Abstract: An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings.Type: GrantFiled: September 16, 2011Date of Patent: June 11, 2013Assignee: United Microelectronics Corp.Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Feng-Yi Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin
-
Publication number: 20130089962Abstract: A semiconductor process includes the following steps. A substrate is provided. A gate structure is formed on the substrate. A spacer is formed on the substrate beside the gate structure. The spacer includes a first spacer and a second spacer located on the external surface of the first spacer. A first etching process is performed to etch and form at least a recess in the substrate beside the spacer and entirely remove the second spacer. The etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer. An epitaxial layer is formed in the recess.Type: ApplicationFiled: October 11, 2011Publication date: April 11, 2013Inventors: Chung-Fu Chang, Shin-Chuan Huang, Yu-Hsiang Hung, Chia-Jong Liu, Pei-Yu Chou, Jyh-Shyang Jenq, Ling-Chun Chou, I-Chang Wang, Ching-Wen Hung, Ted Ming-Lang Guo, Chun-Yuan Wu
-
Patent number: 8324038Abstract: A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.Type: GrantFiled: November 20, 2008Date of Patent: December 4, 2012Assignee: United Microelectronics Corp.Inventors: Pei-Yu Chou, Shih-Fang Tzou, Jiunn-Hsiung Liao
-
Patent number: 8310012Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer.Type: GrantFiled: April 13, 2010Date of Patent: November 13, 2012Assignee: United Microelectronics Corp.Inventors: Guang-Yaw Hwang, Yu-Ru Yang, Jiunn-Hsiung Liao, Pei-Yu Chou
-
Publication number: 20120270403Abstract: A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.Type: ApplicationFiled: June 28, 2012Publication date: October 25, 2012Inventors: Feng-Yi Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin, Po-Chao Tsao
-
Patent number: 8293639Abstract: A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.Type: GrantFiled: February 16, 2009Date of Patent: October 23, 2012Assignee: United Microelectronics Corp.Inventors: Feng-Yih Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin
-
Publication number: 20120220113Abstract: The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.Type: ApplicationFiled: February 24, 2011Publication date: August 30, 2012Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Shui-Yen Lu, Pei-Yu Chou, Shin-Chi Chen, Jiunn-Hsiung Liao, Shang-Yuan Tsai, Chan-Lon Yang, Teng-Chun Tsai, Chun-Hsien Lin
-
Patent number: 8236702Abstract: A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.Type: GrantFiled: March 5, 2008Date of Patent: August 7, 2012Assignee: United Microelectronics Corp.Inventors: Feng-Yi Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin, Po-Chao Tsao