Abstract: A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set.

Abstract: A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory.

Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Abstract: In an integrated circuit having a plurality of modules and/or submodules that each performs a substantially same function, defective modules and/or submodules are determined by creating a test signature from an input test pattern. The output of each module and/or submodule is compared with the test signature and defective modules to identify defective modules and/or submodules. The identity of defective modules/submodules is stored on the integrated circuit for subsequent use by a customer. Integrated circuits having one or more defective modules/submodules are sold to customers with full disclosure of which modules/submodules are defective, thereby improving the yield associated with the product. Pricing of the product is discounted for products with less than full functionality.

Abstract: In one form a memory and method thereof has a memory array having a plurality of memory cells. A bit line precharge operation is based on a clock edge of an external clock signal. A word line is selected after the beginning of the precharge operation. A sense operation is begun after enabling the word line, where the sense operation is for sensing a logic state of a memory cell. A data bit is output from the memory array corresponding to the sensed logic state of the memory cell. In one form the bit line precharge operation further comprises the bit line precharge operation having a predetermined duration that is independent of the clock signal, and the sense operation begins a predetermined delay time after enabling the word line, the sense operation having a variable duration.

Abstract: An integrated circuit comprising a plurality of circuits is provided. The integrated circuit further comprises a plurality of power circuits, wherein each of the plurality of power circuits can supply a selected voltage to at least one of the plurality of circuits.

Abstract: A testing system includes a tester probe and a plurality of integrated circuits. Tests are broadcast to the plurality of integrated circuits using carrierless ultra wideband (UWB) radio frequency (RF). All of the plurality of integrated circuits receive, at the same time, test input signals by way of carrierless UWB RF and all of the plurality of integrated circuits run tests and provide results based on the test input signals. Thus, the plurality of integrated circuits are tested simultaneously which significantly reduces test time. Also the tests are not inhibited by physical contact with the integrated circuits.

Abstract: An integrated circuit has a group of cores that communicate with a packet switch using carrierless ultra wideband (UWB) radio frequency (RF) signaling. The packet switch communicates outside the integrated circuit using optical signaling. The carrierless UWB provides for high frequency communication and processing without requiring additional space for interconnects. No special paths are necessary because the signals used by the cores for communicating with the packet switch are RF signals therefore they can be broadcast by the packet switch and be received by a plurality of cores. No conductor line or waveguide is required. Because the signals are carrierless, they can be transmitted with low power. With multiple cores providing information to the switch, the total information being received may exceed the capacity of the RF bandwidth so an external optical interface is provided to multiplex information provided via carrierless UWB RF signals by a plurality of cores.

Abstract: An integrated circuit die has a transistor circuitry section for implementing information handling operations. Optical circuitry is within the single semiconductor die. The optical circuitry includes a laser transmitter and is operably coupled to the transistor circuitry section. The transistor circuitry section originates information. The optical circuitry transmits the information in a laser beam through a wave guide to the edge of the integrated circuit die.

Abstract: A free-space communication system and method of operation includes a first communication device physically coupled to a substrate and having an optical transmitter for communicating information. A second communication device is physically coupled to the substrate and has an optical receiver for communicating information. An adjustable optical beam deflector is physically coupled to the substrate for optically coupling the first communication device and the second communication device via an optical beam including a free-space optical portion. A feedback system includes a non-optical communication link for receiving information regarding the optical beam. The feedback system controls the adjustable optical beam deflector to direct the optical beam to improve the quality of an optical link incorporating the optical beam.

Abstract: A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.

Abstract: A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.

Abstract: A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set.

Abstract: A double-rate memory has an array of single word line memory cells arranged in rows and columns. The single word line memory cells provide and store data via a first port. Addressing and control circuitry is coupled to the array of single word line memory cells. The addressing and control circuitry receives an address enable signal to initiate an access of the array whereby an address is received, decoded, and corresponding data retrieved or stored. Edge detection circuitry receives a memory clock and provides the address enable signal upon each rising edge and each falling edge of the memory clock to perform two memory operations in a single cycle of the memory clock. A memory operation includes addressing the memory and storing data in the memory or retrieving and latching data from the memory. In another form a double-rate dual port memory permits two independent read/write memory accesses in a single memory cycle.

Abstract: A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a first power supply terminal, is provided. The memory further comprises a first gating transistor coupled between a second power supply terminal and the second power supply node, the first gating transistor receiving a first write enable signal that gates the gating transistor to a non-conductive condition during a write of the first pair of cross-coupled inverters. The memory further comprises a first pass transistor coupled to the first word line, the first input/output node, and the first bit line and a second pass transistor coupled to the first word line, the second input/output node, and the second bit line.

Abstract: A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Abstract: An integrated circuit comprising a plurality of circuits is provided. The integrated circuit further comprises a plurality of power circuits, wherein each of the plurality of power circuits can supply a selected voltage to at least one of the plurality of circuits.

Abstract: In one form a memory and method thereof has a memory array having a plurality of columns of bit lines and a plurality of intersecting rows of word lines. Control circuitry is coupled to the memory array for successively accessing predetermined bit locations in the memory array during successive memory cycles. The control circuitry senses data within the memory array at a beginning of a predetermined memory cycle. Timing of the memory cycle is determined from a single external clock edge of a memory system clock. During a single memory cycle the memory initially performs the function of sensing followed by at least the functions of precharging the bit lines, addressing and developing a signal to be sensed. In one form each of the successive memory cycles is a period of time of no more than a single period of the memory system clock.