Abstract: To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad.

Abstract: To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.

Abstract: Designs and methodologies related to attenuators having a thin-film resistor assembly are disclosed. In some embodiments, the thin-film assembly can include a first and second thin-film resistor, each having a main portion with an input end and an output end. The input end of the first thin-film resistor is interconnected to the input end of the second thin-film resistors, and the output end of the first thin-film resistor is interconnected to the output end of the second thin-film resistor. The first and second thin-film resistors are disposed relative to one another so as to define a separation. The separation region reduces the likelihood of hot spot regions forming at or near the center of the thin-film structure and improves power handling capability for a given resistor width. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of fabrication.

Abstract: A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.

Abstract: A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT.

Abstract: Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET.

Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.

Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.

Abstract: A hyperabrupt diode structure includes a substrate formed from a low-ohmic contact material, a graded semiconductor layer comprising gallium arsenide, an offset layer comprising indium gallium phosphide over the graded semiconductor layer, a contact layer comprising gallium arsenide over the offset layer, a first electrical contact on the substrate, the first electrical contact forming a cathode of the hyperabrupt diode structure, and a second electrical contact over the contact layer, the second electrical contact forming an anode of the hyperabrupt diode structure.

Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.

Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.

Abstract: A circuit and process is provided for protecting a device from the detrimental effects of electro-static discharge (ESD). The circuit includes an ESD breakdown device that is used to activate a current drawdown device. When a voltage exceeding the ESD breakdown device's breakdown voltage is applied, a signal is generated that causes the current drawdown device to pump current to ground. In this way, the effects of the ESD charge are substantially reduced. In one example, the ESD breakdown device is a reverse biased diode, and the current drawdown circuit includes a Darlington circuit. When an ESD surge causes the diode to breakdown, a signal is applied to the Darlington circuit, which pumps the ESD current safely to ground.

Abstract: According to one exemplary embodiment, a gallium arsenide heterojunction bipolar transistor comprises a collector layer and a first spacer layer situated over the collector layer, where the first spacer layer is a high-doped P+ layer. For example, the first spacer layer may comprise GaAs doped with carbon. The gallium arsenide heterojunction bipolar transistor further comprises a base layer situated over the first spacer layer. The base layer may comprise, for example, a concentration of indium, where the concentration of indium is linearly graded in the base layer. The base layer may comprise InGaAsN, for example. The gallium arsenide heterojunction bipolar transistor further comprises an emitter layer situated over the base layer. The emitter layer may comprise, for example, InGaP.

Abstract: According to one exemplary embodiment, a BiFET situated on a substrate comprises an emitter layer segment situated over the substrate, where the emitter layer segment comprises a semiconductor of a first type. The HBT further comprises a first segment of an etch stop layer, where the first segment of the etch stop layer comprises InGaP. The BiFET further comprises a FET situated over the substrate, where the FET comprises source and drain regions, where a second segment of the etch stop layer is situated under the source and drain regions, and where the second segment of the etch stop layer comprises InGaP. The FET further comprises a semiconductor layer of a second type situated under the second segment of the etch stop layer. The etch stop layer increases linearity of the FET and does not degrade electron current flow in the HBT.

Abstract: According to one exemplary embodiment, a gallium arsenide heterojunction bipolar transistor comprises a collector layer and a first spacer layer situated over the collector layer, where the first spacer layer is a high-doped P+ layer. For example, the first spacer layer may comprise GaAs doped with carbon. The gallium arsenide heterojunction bipolar transistor further comprises a base layer situated over the first spacer layer. The base layer may comprise, for example, a concentration of indium, where the concentration of indium is linearly graded in the base layer. The base layer may comprise InGaAsN, for example. The gallium arsenide heterojunction bipolar transistor further comprises an emitter layer situated over the base layer. The emitter layer may comprise, for example, InGaP.

Abstract: A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e.g., GaAs), and a narrow bandgap collector region (e.g., InGaP). The higher electric field is supported in the wide bandgap region, thereby increasing breakdown voltage and reducing offset voltage. At the same time, the use of wide bandgap material in the depleted portion of the collector, and a higher mobility material toward the end and outside of the depletion region, reduces series resistance as well as knee voltage.

Abstract: In one disclosed embodiment, a collector is deposited and a base is grown on the collector, for example, by epitaxially depositing either silicon or silicon-germanium. An emitter is fabricated on the base followed by implant doping an extrinsic base region. For example, the extrinsic base region can be implant doped using boron. The extrinsic base region doping diffuses out during subsequent thermal processing steps in chip fabrication, creating an out diffusion region in the device, which can adversely affect various operating characteristics, such as parasitic capacitance and linearity. The out diffusion is controlled by counter doping the out diffusion region. For example, the counter doped region can be implant doped using arsenic or phosphorous. Also, for example, the counter doped region can be formed using tilt implanting or, alternatively, by implant doping the counter doped region and forming a spacer on the base prior to implanting the extrinsic base region.

Abstract: In one disclosed embodiment, a collector is deposited and a base is grown on the collector, for example, by epitaxially depositing either silicon or silicon-germanium. An emitter is fabricated on the base followed by implant doping an extrinsic base region. For example, the extrinsic base region can be implant doped using boron. The extrinsic base region doping diffuses out during subsequent thermal processing steps in chip fabrication, creating an out diffusion region in the device, which can adversely affect various operating characteristics, such as parasitic capacitance and linearity. The out diffusion is controlled by counter doping the out diffusion region. For example, the counter doped region can be implant doped using arsenic or phosphorous. Also, for example, the counter doped region can be formed using tilt implanting or, alternatively, by implant doping the counter doped region and forming a spacer on the base prior to implanting the extrinsic base region.