Patents by Inventor Peter J. Zampardi

Peter J. Zampardi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170257070
    Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier die, a first bonding pad on a conductive trace, and a second bonding pad on a conductive trace. The die includes an on-die passive device and a power amplifier. The first bonding pad is electrically connected to the on-die passive device by a first wire bond. The second bonding pad is in a conductive path between the first bonding pad and a radio frequency output of the power amplifier module. The second bonding pad includes a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer and bonded to a second wire bond that is electrically connected to an output of the power amplifier. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Application
    Filed: April 7, 2017
    Publication date: September 7, 2017
    Inventors: Hardik Bhupendra Modi, Sandra Louise Petty-Weeks, Hongxiao Shao, Weimin Sun, Peter J. Zampardi, JR., Guohao Zhang
  • Patent number: 9755592
    Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and tantalum nitride terminated through wafer via. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. A metal layer in the tantalum nitride terminated through wafer via is included in an electrical connection between the power amplifier on a front side of a substrate and a conductive layer on a back side of the substrate. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 5, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Hsiang-Chih Sun, Hong Shen, Mehran Janani, Jens Albrecht Riege
  • Patent number: 9741834
    Abstract: A transistor includes a sub-collector, a base, a collector between the sub-collector and the base, and an emitter on the base opposite the collector. The collector includes a first region adjacent to the base and a second region between the first region and the sub-collector. The first region has a graduated doping profile such that a doping concentration of the first region decreases in proportion to a distance from the base. The second region has a substantially constant doping profile. By providing the collector with a doping profile as described, the linearity of the transistor is significantly improved while maintaining the radio frequency (RF) gain thereof.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: August 22, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Peter J. Zampardi, Brian G. Moser, Jing Zhang, Thomas James Rogers
  • Publication number: 20170236925
    Abstract: The present disclosure relates to a semiconductor device with multiple heterojunction bipolar transistors (HBTs) that have different emitter ballast resistances. The disclosed semiconductor device includes a substrate, a first HBT and a second HBT formed over the substrate. The first HBT includes a first collector, a first base over the first collector, a first emitter over the first base, and a first cap structure over the first emitter. The second HBT includes a second collector, a second base over the second collector, a second emitter over the second base, and a second cap structure over the second emitter. Herein, the first cap structure is different from the second cap structure, such that a first emitter ballast resistance from the first cap structure is at least 1.5 times greater than a second emitter ballast resistance from the second cap structure.
    Type: Application
    Filed: August 15, 2016
    Publication date: August 17, 2017
    Inventors: Peter J. Zampardi, Brian G. Moser, Thomas James Rogers
  • Publication number: 20170221880
    Abstract: A device includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage can be applied to the back gate of the FET.
    Type: Application
    Filed: November 10, 2016
    Publication date: August 3, 2017
    Inventors: Bin Li, Peter J. Zampardi, JR., Andre G. Metzger
  • Patent number: 9722058
    Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 1, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Kai Hay Kwok
  • Publication number: 20170207125
    Abstract: A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 20, 2017
    Inventors: Peter J. Zampardi, JR., Hsiang-Chih Sun
  • Patent number: 9698137
    Abstract: Electrostatic Discharge (ESD) protection using lateral surface Schottky diodes is disclosed. In one embodiment, a Metal-Insulator-Metal (MIM) capacitor with ESD protection comprises a group III-V substrate, a first metal layer contacting the substrate, an insulation layer formed over the first metal layer, and a second metal layer formed over the insulation layer and also contacting the substrate. A MIM capacitor is formed by overlapping portions of the first metal layer, the insulation layer, and the second metal layer. First and second Schottky diodes are formed where the first and second metal layers, respectively, contact the substrate, such that the cathodes of the Schottky diodes are electrically connected to one another and the anodes of the Schottky diodes are electrically connected to the respective overlapping portions of the first and second metal layers.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 4, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Peter J. Zampardi, Brian G. Moser, Michael Meeder, Venkata Chivukula
  • Patent number: 9692357
    Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier die including a power amplifier configured to amplify a radio frequency (RF) signal, the power amplifier including a heterojunction bipolar transistor (HBT) and a p-type field effect transistor (PFET), the PFET including a semiconductor segment that includes substantially the same material as a layer of a collector of the HBT, the semiconductor segment corresponding to a channel of the PFET; a load line electrically connected to an output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the RF signal; and a harmonic termination circuit electrically connected to the output of the power amplifier and configured to terminate at a phase corresponding to a harmonic frequency of the RF signal. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: June 27, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Dinhphuoc Vu Hoang, Hardik Bhupendra Modi, Hsiang-Chih Sun, Peter J. Zampardi, Jr., Guohao Zhang
  • Patent number: 9673271
    Abstract: A method of making a capacitor with reduced variance comprises providing a bottom plate in a first metal layer, a first dielectric material over the bottom plate, and a middle plate in a second metal layer to form a first capacitor. The method also comprises measuring the capacitance of the first capacitor, and determining whether to couple none, one, or both of a second capacitor and a third capacitor in parallel with the first capacitor. The method may further comprise the steps of providing a second dielectric material over the middle plate, and providing a first top plate and a second top plate in a third metal layer to form the second capacitor, and a third capacitor. Electrical connections may be formed to couple one or both of the second capacitor and the third capacitor in parallel with the first capacitor based on the measured value of the first capacitor.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: June 6, 2017
    Assignee: Qorvo US, Inc.
    Inventors: Peter J. Zampardi, Brian Moser
  • Patent number: 9660584
    Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier; a wire bond pad electrically connected to the power amplifier, the wire bond pad including a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer; and a conductive trace having a top surface with a plated portion and an unplated portion surrounding the plated portion, the wire bond pad being disposed over the plated portion. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 23, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hardik Bhupendra Modi, Sandra Louise Petty-Weeks, Hongxiao Shao, Weimin Sun, Peter J. Zampardi, Jr., Guohao Zhang
  • Publication number: 20170104055
    Abstract: A method of making a capacitor with reduced variance comprises providing a bottom plate in a first metal layer, a first dielectric material over the bottom plate, and a middle plate in a second metal layer to form a first capacitor. The method also comprises measuring the capacitance of the first capacitor, and determining whether to couple none, one, or both of a second capacitor and a third capacitor in parallel with the first capacitor. The method may further comprise the steps of providing a second dielectric material over the middle plate, and providing a first top plate and a second top plate in a third metal layer to form the second capacitor, and a third capacitor. Electrical connections may be formed to couple one or both of the second capacitor and the third capacitor in parallel with the first capacitor based on the measured value of the first capacitor.
    Type: Application
    Filed: October 12, 2015
    Publication date: April 13, 2017
    Inventors: Peter J. Zampardi, Brian Moser
  • Publication number: 20170103976
    Abstract: Electrostatic Discharge (ESD) protection using lateral surface Schottky diodes is disclosed. In one embodiment, a Metal-Insulator-Metal (MIM) capacitor with ESD protection comprises a group III-V substrate, a first metal layer contacting the substrate, an insulation layer formed over the first metal layer, and a second metal layer formed over the insulation layer and also contacting the substrate. A MIM capacitor is formed by overlapping portions of the first metal layer, the insulation layer, and the second metal layer. First and second Schottky diodes are formed where the first and second metal layers, respectively, contact the substrate, such that the cathodes of the Schottky diodes are electrically connected to one another and the anodes of the Schottky diodes are electrically connected to the respective overlapping portions of the first and second metal layers.
    Type: Application
    Filed: June 27, 2016
    Publication date: April 13, 2017
    Inventors: Peter J. Zampardi, Brian G. Moser, Michael Meeder, Venkata Chivukula
  • Publication number: 20170069584
    Abstract: To reduce radio frequency losses during operation of a radio frequency integrated circuit module, the radio frequency integrated circuit module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the radio frequency current to flow around the high-resistivity material, which reduces the radio frequency signal loss associated with the high resistivity plating material.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 9, 2017
    Inventors: Weimin Sun, Peter J. Zampardi, JR., Hongxiao Shao
  • Patent number: 9559096
    Abstract: A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: January 31, 2017
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Peter J. Zampardi, Hsiang-Chih Sun
  • Publication number: 20170019076
    Abstract: The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.
    Type: Application
    Filed: July 21, 2016
    Publication date: January 19, 2017
    Inventors: David Steven Ripley, Philip John Lehtola, Peter J. Zampardi, JR., Hongxiao Shao, Tin Myint Ko, Matthew Thomas Ozalas
  • Publication number: 20170005184
    Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 5, 2017
    Inventors: Peter J. ZAMPARDI, Jr., Kai Hay Kwok
  • Publication number: 20160380594
    Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to provide a radio frequency signal at an output, an output matching network coupled to the output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the radio frequency signal, and a harmonic termination circuit coupled to the output of the power amplifier. The power amplifier is included on a power amplifier die. The output matching network can include a first circuit element electrically connected to an output of the power amplifier by way of a pad on a top surface of a conductive trace, in which the top surface has an unplated portion between the pad the power amplifier die. The harmonic termination circuit can include a second circuit element. The first and second circuit elements can have separate electrical connections to the power amplifier die. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Application
    Filed: September 8, 2016
    Publication date: December 29, 2016
    Inventors: Weimin Sun, Peter J. Zampardi, JR., Hongxiao Shao, Guohao Zhang, Hardik Bhupendra Modi, Dinhphuoc Vu Hoang
  • Publication number: 20160379944
    Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and an RF transmission line electrically coupled to an output of the power amplifier. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. The RF transmission line includes a nickel layer with a thickness that is less than 0.5 um, a conductive layer under the nickel layer, a palladium layer over the nickel layer, and a gold layer over the palladium layer. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Application
    Filed: September 8, 2016
    Publication date: December 29, 2016
    Inventors: Peter J. Zampardi, JR., Hsiang-Chih Sun, Sandra Louise Petty-Weeks, Guohao Zhang, Hardik Bhupendra Modi
  • Publication number: 20160380602
    Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and tantalum nitride terminated through wafer via. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. A metal layer in the tantalum nitride terminated through wafer via is included in an electrical connection between the power amplifier on a front side of a substrate and a conductive layer on a back side of the substrate. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Application
    Filed: September 8, 2016
    Publication date: December 29, 2016
    Inventors: Peter J. Zampardi, JR., Hsiang-Chih Sun, Hong Shen, Mehran Janani, Jens Albrecht Riege